Investigation on Power, Delay and Area optimization of XOR Gate

Abstract

Nowadays a mobile computing and multimedia applications are need for high-performance reduced size and low-power devices. The multiplication is major operation in any signal processing applications. In any multiplier architecture, adder is one of the major processing elements. In which XOR is the basic block of an adder and multiplier. In this paper, a various design styles of XOR Gate have been surveyed and simulated using Microwind tool. In that XOR gate was analyzed the power using the different styles. They are conventional XOR gate, Pass transistor logic based EX-OR gate, Static inverter based EX-OR gate, Transmission Gate based EX-OR Gate, EX-OR Gate based on 8 & 6 Transistor & and Modified version of EX-OR Gate The CMOS circuit layout was created and simulated in Microwind software. In that the proposed XOR-based circuit has 40.17% of power consumption has improved &14.28 % of area in-terms of number of transistor improved as compare to modified version of EX-OR Gate design.