Investigation of Tunneling FET Device Designs for Improving Circuit Switching Performance and Energy

Chen, Y.N.; Fan, Ming-Long; Hu, Vita Pi‐Ho; Su, Pin; Chuang, Ching-Te

doi:10.7567/ssdm.2013.ps-3-15

Cited by 4 publications

(3 citation statements)

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“…(b) Enhanced Miller Capacitance: Normally, the total gate capacitance (C gg ) in a TFET is dominated by the drain component (C gd ). This is due to the band misalignment at the source channel interface and influence of V ds on the movement of carriers across the drain junction [93]. This increases the total Miller capacitance of the device and results in undesirable spikes in the transient characteristics of the implemented circuit thus creating a surge in the dynamic power dissipation.…”

Section: Synthesis Perspectivementioning

confidence: 99%

“…To actualize p and n-TFETs with comparable drive strengths, the total Miller capacitance of the device must be considerably reduced by using gate engineering techniques. The use of hetero dielectric under the gate metal, known as Dual Oxide technique (DOX) [93] increases the total drain current (using high-K oxide near source) and solves the current degradation in the internal nodes while stacking (shown in figure 7 barrier at the drain and lowers gate-drain capacitance significantly [98]. The performance improvement can be seen in terms of energy delay product in figure 7(c).…”

Section: (C) Improved Complementary Tfet Designmentioning

confidence: 99%

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More-than-moore steep slope devices for higher frequency switching applications: a designer’s perspective

Chowdhury,

Sarkar,

Mahapatra

et al. 2024

Phys. Scr.

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The progress in IC miniaturization dictated by Moore’s Law has taken a leap from mere circuit integration to IoT enabled System-on-Chip (SoC) deployments. Such systems are connoted by contemporary advancements in the semiconductor industry roadmaps namely, ‘More-Moore’ and ‘More-than-Moore’ (MtM). For meaningful integration of digital and non-digital blocks, a power performance tradeoff is essential for maximum and fruitful utilization of the silicon area. Using the techniques under the MtM nomenclature allows the use of unconventional steep slope devices like Tunneling FETs, Negative Capacitance (NC) FETs, Gate-all-around FETs (GAA) and FinFETs etc., which can exhibit reasonable performance with lower supply voltages. Following the Device Technology Co-optimization (DTCO) and System Technology Co optimization (STCO) the advanced 3D heterogenous integration technologies allow sensors, analog/mixed signal and passive components to be assimilated within the same package as the CMOS blocks. Appropriate device engineering techniques like multi-gate architectures, vertical stacking transistors, compound semiconductors and alternate carrier transport phenomena are required to improve the current drive and scaling performance of advanced CMOS devices. CMOS based codesign is essential to realize new topologies for energy economical computation, sensing and information processing as the beyond CMOS steep slope devices are independently incapable of replacing conventional bulk CMOS devices. This article presents a detailed qualitative review of the various aspects of MtM beyond CMOS steep slope switches and their prospective integration technologies. For system level integration, various aspects of device performance and optimizations, related device-circuit interactions, dielectric technologies at the advance nanometer nodes have been probed into. Additionally, novel circuit topologies, synthesis algorithms and processor level performance evaluation using steep slope switches have been investigated. An exclusive compact overview for contemporary insights into integrated device-system development methodology and its performance evaluation is presented.

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Section: Synthesis Perspectivementioning

confidence: 99%

Section: (C) Improved Complementary Tfet Designmentioning

confidence: 99%

More-than-moore steep slope devices for higher frequency switching applications: a designer’s perspective

Chowdhury,

Sarkar,

Mahapatra

et al. 2024

Phys. Scr.

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“…From circuit point of view, the Miller capacitance of TFET device is of particular importance and should be reduced. In our previous study [8], the device design techniques for improving the device characteristic and reducing of TFET device are investigated. Among the techniques, the Dual Oxide (DOX) approach, where low-gate dielectric is used near the drain side to reduce the Miller capacitance, provides better improvements in both the delay and dynamic energy.…”

Section: Introductionmentioning

confidence: 99%

Evaluation of Sub-0.2 V High-Speed Low-Power Circuits Using Hetero-Channel MOSFET and Tunneling FET Devices

Chen

Fan

et al. 2014

IEEE Trans. Circuits Syst. I

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This paper investigates the feasibility of sub-0.2 V high-speed low-power circuits with hetero-channel MOSFET and emerging Tunneling FET (TFET) devices. First, the device designs and characteristics of hetero-channel MOSFET and TFET devices are discussed and compared. Due to the significant leakage current of ultra-low hetero-channel MOSFET devices, assist-circuits are required for hetero-channel MOSFET-based circuits to operate at 0.2 V. Second, the delay, dynamic energy and the Standby power of hetero-channel TFET-based and MOSFET-based logic circuits including Inverter, NAND, BUS Driver, and Latch are analyzed and evaluated. The results indicate that hetero-channel TFET-based circuits with Dual Oxide (DOX) device design to reduce the Miller capacitance provide the potential to achieve high-speed low-power operation at , while the use of assist-circuits in MOSFET-based design improves the delay and dynamic energy at the expense of increased device count, circuit area, and large Standby and sleep-mode leakage power. Finally, the impacts of temperature and process variations on TFET-based and MOSFET-based logic circuits are discussed. Index Terms-Hetero-channel MOSFET, high-speed, lowpower, tunnel FET.1549-8328 he conducted his doctoral and postdoctoral research in Silicon-On-Insulator (SOI) devices at Berkeley. He was also one of the major contributors to the unified BSIMSOI model, the first industrial standard SOI MOSFET model for circuit design. Since August 2003, he has been with the Department of Electronics Engineering, NCTU, where he is currently a Professor. His research interests include silicon-based nanoelectronics, modeling and design for exploratory CMOS devices for ultra-low-power applications, and circuit-device interaction and co-optimization in nanoscale CMOS. He has authored or coauthored over 70 refereed journal papers and 100 conference papers regarding his research interests. Ching-Te Chuang

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Review of Emerging Tunnel FET Structures

Bag

Bhowmick

2021

Lecture Notes in Electrical Engineering

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Investigation of Tunneling FET Device Designs for Improving Circuit Switching Performance and Energy

Cited by 4 publications

References 0 publications

More-than-moore steep slope devices for higher frequency switching applications: a designer’s perspective

More-than-moore steep slope devices for higher frequency switching applications: a designer’s perspective

Evaluation of Sub-0.2 V High-Speed Low-Power Circuits Using Hetero-Channel MOSFET and Tunneling FET Devices

Review of Emerging Tunnel FET Structures

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