Investigation of the Off-State Degradation in Advanced FinFET Technology—Part I: Experiments and Analysis

Sun, Zixuan; Wang, Runsheng; Zhang, Lining; Zhang, Jiayang; Zhang, Zuodong; Song, Jiahao; Wang, Da; Ji, Zhigang; Huang, Ru

doi:10.1109/ted.2023.3239585

Cited by 7 publications

(5 citation statements)

References 33 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…This degradation phenomenon is explained as secondary carriers being captured by traps near the drain region, causing a decrease in effective channel length, resulting in reduced threshold voltage and an increase in leakage current. However, in advanced FinFETs, off-state degradation is considered a complex phenomenon involving multiple electrical traps and mechanisms [ 100 , 101 ]. As shown in Figure 11 , the non-monotonic shift of threshold voltage caused by the contribution of multiple electrical traps has been observed in FinFETs.…”

Section: Mixed-mode Reliability Mechanismsmentioning

confidence: 99%

“…For HCD, the phenomenon involves the breakage of Si-H bonds by high-energy hot carriers, forming interface states that induce degradation in the threshold voltage and mobility [ 56 , 57 , 58 ]. As device nodes advance and carrier energy decreases, electron–electron scattering (EES) and multiple vibration excitation (MVE) mechanisms have been proposed to explain the contributions of low-energy carriers to HCD [ 59 , 60 , 61 ]. Simultaneously, the contribution of oxide trap-induced degradation in HCD becomes more pronounced, especially in FinFET devices, where HCD is considered a combined effect of oxide traps and interface states [ 62 , 63 ].…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

The Understanding and Compact Modeling of Reliability in Modern Metal–Oxide–Semiconductor Field-Effect Transistors: From Single-Mode to Mixed-Mode Mechanisms

Sun,

Chen,

Zhang

et al. 2024

Micromachines

Self Cite

View full text Add to dashboard Cite

With the technological scaling of metal–oxide–semiconductor field-effect transistors (MOSFETs) and the scarcity of circuit design margins, the characteristics of device reliability have garnered widespread attention. Traditional single-mode reliability mechanisms and modeling are less sufficient to meet the demands of resilient circuit designs. Mixed-mode reliability mechanisms and modeling have become a focal point of future designs for reliability. This paper reviews the mechanisms and compact aging models of mixed-mode reliability. The mechanism and modeling method of mixed-mode reliability are discussed, including hot carrier degradation (HCD) with self-heating effect, mixed-mode aging of HCD and Bias Temperature Instability (BTI), off-state degradation (OSD), on-state time-dependent dielectric breakdown (TDDB), and metal electromigration (EM). The impact of alternating HCD-BTI stress conditions is also discussed. The results indicate that single-mode reliability analysis is insufficient for predicting the lifetime of advanced technology and circuits and provides guidance for future mixed-mode reliability analysis and modeling.

show abstract

Section: Mixed-mode Reliability Mechanismsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

The Understanding and Compact Modeling of Reliability in Modern Metal–Oxide–Semiconductor Field-Effect Transistors: From Single-Mode to Mixed-Mode Mechanisms

Sun,

Chen,

Zhang

et al. 2024

Micromachines

Self Cite

View full text Add to dashboard Cite

show abstract

“…Miniaturizing integrated circuits while increasing functionality has necessitated the aggressive scaling of MOSFET devices [1], requiring these transistors to achieve high performance, at less prone to short-channel effects [13,14] and requires low power [15,16], at the cost of increased fabrication complexity [17] compared to the planar version of these architectures such as double-gate silicon-on-insulator (DG SOI) MOSFET. Despite being planar, these DG-SOI MOSFET are more scalable to channel lengths of 10 nm without observing significant short-channel effects [18,19], which is found to be possible due to aggressive scaling of the oxide thickness and channel thickness.…”

Section: Introductionmentioning

confidence: 99%

Band-structure based electrostatics model for ultra-thin-body double-gate silicon-on-insulator MOS devices

Mishra

Kansal

Solanki

et al. 2023

J. Phys. D: Appl. Phys.

View full text Add to dashboard Cite

The effect of Quantum Confinement has become significant in terms of its impact on the scalability and electrostatics of Ultra-Thin-Body Double-Gate MOSFETs. In this paper, we present a simplified model to account for the effect of quantum confinement, considering the contribution of the ground-state and the first excited state of the conduction band, on the electron carrier concentration, which when incorporated into the 1-D Poisson's equation, enables the determination of the electrostatic potential. We establish the accuracy of the proposed model, over a wide range of process and electrical parameters, through aggressively benchmarking the electrostatics parameters obtained from the proposed model with results from the sp3d5s* Tight-Binding Model (TBM), over a wide range of device temperatures. Furthermore, a simplified model for the integrated channel charge density is shown in the form of a diffusion layer charge where the thickness and potential of this layer, while being gate voltage dependent, enables the channel charge density obtained from the model to agree well with results from TBM. Through this physics based and accurate model for the integrated charge, a simplified understanding of the gate capacitance is shown as a series combination of the diffusion layer capacitance, strong-inversion capacitance and oxide capacitance, which includes the effects of structural confinement as well as charge confinement at low and high gate voltages, respectively.

show abstract

“…It is expensive to monopolise such a test bench with access to the transistor, so most of the degradation measurements are carried out for less than 10,000 s (≈3 h) [ 10 , 12 , 16 , 17 ]. In order to observe degradation over a short test period, the ageing conditions applied are far from operational conditions.…”

Section: Introductionmentioning

confidence: 99%

“…The FinFET, a transistor with an out-of-plane fin-shaped channel, is widely used in the latest generation of digital circuits with nodes down to five nanometers [1]. The reliability of a digital circuit under ageing effects is affected by degradation at the transistor level [2] (chapter 15) but also by defects at the packaging level [2] (chapter 16). This article will focus on transistor degradation without considering the other mechanisms.…”

Section: Introduction 1contextmentioning

confidence: 99%

Degradation Measurement and Modelling under Ageing in a 16 nm FinFET FPGA

Sobas,

Marc

2023

Micromachines

View full text Add to dashboard Cite

Most of the latest generation of integrated circuits use FinFET transistors for their performance, but what about their reliability? Does the architectural evolution from planar MOSFET to FinFET transistor have any effect on the integrated circuit reliability? In this article, we present a test bench we have developed to age and measure the degradation of 5103 ring oscillators (ROs) implemented in nine FPGAs with 16nm FinFET under different temperature and voltage conditions (Vnom≤Vstress≤1.3Vnom and 25°C≤Tstress≤115°C) close to operational conditions in order to predict reliability regarding degradation mechanisms at the transistor scale (BTI, HCI and TDDB) as realistically as possible. By comparing our initial RO measurements and the data extracted from Vivado, we will show that the performance of the nine FPGAs is between 50% and 70% of the best performance expected by Vivado. After 8000 h of ageing, we will see that the relative degradations of the RO are a maximum of 1%, which is a first indicator proving the FPGAs’ good reliability. By comparing our results with similar studies on 28 nm MOSFET FPGAs, we will reveal that 16 nm FinFET FPGAs are more reliable. To be implemented in an FPGA, an RO uses logic resources (LUT) and routing resources. We will show that degradation in the two types of resources is different. For this reason, we will present a method for separating degradations in logical and routing resources based on RO degradation measures. Finally, we will model rising and falling edge propagation time degradations in an FPGA as a function of time, temperature, voltage, signal duty cycle and resources used in the FPGA.

show abstract

Investigation of the Off-State Degradation in Advanced FinFET Technology—Part I: Experiments and Analysis

Cited by 7 publications

References 33 publications

The Understanding and Compact Modeling of Reliability in Modern Metal–Oxide–Semiconductor Field-Effect Transistors: From Single-Mode to Mixed-Mode Mechanisms

The Understanding and Compact Modeling of Reliability in Modern Metal–Oxide–Semiconductor Field-Effect Transistors: From Single-Mode to Mixed-Mode Mechanisms

Band-structure based electrostatics model for ultra-thin-body double-gate silicon-on-insulator MOS devices

Degradation Measurement and Modelling under Ageing in a 16 nm FinFET FPGA

Contact Info

Product

Resources

About