Investigation of switching and inverter characteristics of Recessed-Source/Drain (Re–S/D) Silicon-on-Insulator (SOI) Feedback Field Effect Transistor (FBFET)

Suddarsi, Sasi Kiran; Dhanaraj, K.J.; Saramekala, Gopi Krishna

doi:10.1016/j.mejo.2023.105855

Cited by 4 publications

(2 citation statements)

References 17 publications

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“…However, the novel devices always results >60 mV/decade due to boltzmann tyranny. 31,32 The change in SS of proposed DM JL Tree-FET is depicted in Fig. 3a for various L g , T NS and W NS .…”

Section: Resultsmentioning

confidence: 99%

Optimizing Device Dimensions for Dual Material Junctionless Tree-FET: A Path to Improved Analog/RF Performance

Beebireddy,

Fatima,

2024

ECS J. Solid State Sci. Technol.

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This comprehensive study delves into the intricate analysis of the electrical and analog/RF performance of the Dual Material (DM) junctionless (JL) Tree-FET. During the optimization process, various DC and analog/RF metrics were taken into account. It is observed that, as the gate length decreases (12 nm to 8 nm), there is an increment in drain induced barrier lowering (DIBL), switching ratio (Ion/Ioff), and subthreshold swing (SS). Conversely, reducing the size of TNS (and WNS) from 10 nm to 5 nm (and 20 nm to 10 nm, respectively) lead to notable improvements, with a 34.4% (21.01%) decrease in SS, 93.19% (58.86%) decrease in DIBL, and 98.6% (41.06%) increase in Ion/Ioff. Furthermore, the analog/RF performance metrics of the device is carefully examined across dimensional variations, revealing significant improvements at the optimal values. Additionally, the study extends to the evaluation of inverter circuit characteristics with DM JL Tree-FET. Remarkably, the static noise margin (SNM) and delay exhibit 337.3 mV and 3.053 ps, respectively, positioning the device as a prime candidate for applications demanding low power consumption and high-frequency operation in future technology nodes.

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Section: Resultsmentioning

confidence: 99%

Optimizing Device Dimensions for Dual Material Junctionless Tree-FET: A Path to Improved Analog/RF Performance

Beebireddy,

Fatima,

2024

ECS J. Solid State Sci. Technol.

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“…The FBFET exhibits an approximately zero slope and hysteresis characteristics [20][21][22]. Various circuits consisting of FBFETs operating as logic [23][24][25], memory circuits [26][27][28], and neuromorphic circuits [29,30] have been presented. In particular, the basic fabrication of the FBFET is based on the complementary metal-oxide-semiconductor (CMOS) technology; therefore, memory circuits configured with the FBFET have received attention as a next-generation memory system considering fabrication costs.…”

Section: Introductionmentioning

confidence: 99%

Investigation of the Electrical Coupling Effect for Monolithic 3-Dimensional Nonvolatile Memory Consisting of a Feedback Field-Effect Transistor Using TCAD

Oh,

2023

Micromachines

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In this study, the electrical characteristics and electrical coupling effect for monolithic 3-dimensional nonvolatile memory consisting of a feedback field-effect transistor (M3D-NVM-FBFET) were investigated using technology computer-aided design. The M3D-NVM-FBFET consists of an N-type FBFET with an oxide–nitride–oxide layer and a metal–oxide–semiconductor FET (MOSFET) in the top and bottom tiers, respectively. For the memory simulation, the programming and erasing voltages were applied at 18 and −18 V for 1 μs, respectively. The memory window of the M3D-NVM-FBFET was 1.98 V. As the retention simulation was conducted for 10 years, the memory window decreased from 1.98 to 0.83 V. For the M3D-NVM-FBFET, the electrical coupling that occurs through an electrical signal in the bottom-tier transistor was investigated. As the thickness of the interlayer dielectric (TILD) decreases from 100 to 10 nm, the change in the VTH increases from 0.16 to 0.87 V and from 0.15 to 0.84 V after the programming and erasing operations, respectively. M3D-NVM-FBFET circuits with a thin TILD of 50 nm or less need to be designed considering electrical coupling.

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Investigation of recessed‐source/drain SOI feedback FET‐based integrate and fire neuron circuit with compact model of threshold switching devices

Suddarsi,

Dhanaraj,

Saramekala

2024

Int J Numerical Modelling

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In this article, the investigation of recessed‐source/drain (Re‐S/D) SOI feedback FET (FBFET)‐based integrate and fire (IF) neuron circuit parameters is presented using a threshold switching device compact model. FBFETs offer high ION and low SS with minimal power consumption, operating efficiently at lower voltages and currents than conventional MOSFETs. Utilizing ION/IOFF ratio and threshold voltage limits (Vt2/Vt1) of the device, a model is developed to mimic hysteresis characteristics, which is then used to implement an IF neuron circuit. Our findings show that altering the Re‐S/D thickness between 0 and 50 nm enhances the ION of the device under study while decreasing hysteresis width. We detected a significant increase in output spike frequency of 46.8% and 65.14% for input current pulse amplitudes of 5 and 20 nA, respectively. Furthermore, increasing the Re‐S/D thickness from 0 to 50 nm led to a significant 29.97% enhancement in spike amplitude. In addition, when using input current pulse amplitudes of 5 and 20 nA, we saw energy savings per spike of 3.36% and 12.7%, respectively. At the same time, there was an increase in power of 8.69% and 9.54%. These enhancements in performance metrics establish our proposed integrate and fire neuron circuit as a promising candidate for efficient neuromorphic system implementation.

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Investigation of switching and inverter characteristics of Recessed-Source/Drain (Re–S/D) Silicon-on-Insulator (SOI) Feedback Field Effect Transistor (FBFET)

Cited by 4 publications

References 17 publications

Optimizing Device Dimensions for Dual Material Junctionless Tree-FET: A Path to Improved Analog/RF Performance

Optimizing Device Dimensions for Dual Material Junctionless Tree-FET: A Path to Improved Analog/RF Performance

Investigation of the Electrical Coupling Effect for Monolithic 3-Dimensional Nonvolatile Memory Consisting of a Feedback Field-Effect Transistor Using TCAD

Investigation of recessed‐source/drain SOI feedback FET‐based integrate and fire neuron circuit with compact model of threshold switching devices

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