Investigation of substrate injection disturb mechanism in high density flash FPGA devices

Abstract

A programming disturb mechanism in the Uniform Channel Program and Erase (UCPE) Flash FPGA cell is investigated. High junction leakage from the inhibit bits on the selected row and unselected columns introduce additional gate disturb failures in a high density Flash FPGA product. It is observed that the total substrate current from the inhibit bits can induce the turn-on of a parasitic bipolar transistor from the neighboring transistor source/drain (S/D) through the substrate injection mechanism with a high field present. These leaky bits impact the overall yield and can later pose reliability concerns. Optimizing the S/D junction profiles with removal of Si defects successfully suppressed the injection induced disturb.