Investigation of interface trap charges and temperature variation in heterostacked-TFET

Vanlalawmpuia, K.; Bhowmick, Brinda

doi:10.1007/s12648-020-01834-z

Cited by 18 publications

(20 citation statements)

References 41 publications

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“…The interfacial trap charge density is evaluated using the following equation: , N t = W × C ox false| q false| , where N t , W , C ox , and q represent the interfacial trap charge density, the hysteresis window measured in the dark, capacitance per unit area of the gate dielectric, and elementary charge, respectively. The hysteresis window gradually increases with the increasing layer of ZnO NPs, suggesting that it may contribute to trapping states at the ZTO and ZnO NPs interface. − …”

Section: Resultsmentioning

confidence: 99%

Dual Light Temporal Coding Modes Enabled by Nanoparticle-Mediated Phototransistors via Gate Bias Modulation for Brain-Inspired Visual Perception

Zeng

Chu

Shih

et al. 2023

ACS Appl. Mater. Interfaces

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The core integration and cooperation of the retina, neurons, and synapses in the visual systems enable humans to effectively sense and process visual information with low power consumption. To mimic the human visual system, an artificial sensory nerve, along with optical sensing�a paired-pulse ratio (PPR) of the light pulse stimulated currents�and neural coding has been developed. For performing the artificial visual perception functions, we consistently reveal the positive and negative correlations between the PPR index and light pulse time interval by applying two consecutive light stimuli with gate voltages of −10 and 5 V, respectively, to a phototransistor. This phototransistor contains a heterostructured channel layer composed of zinc-oxide nanoparticles (ZnO NPs) interconnected with a solution-processed zinc−tin oxide (ZTO) film. The oxygen adsorption and desorption on the ZnO NP surface under light illumination are responsible for the positive-sloped PPR; the electron trapping effect at the ZnO NP/SiO 2 interface is attributed to the negative-sloped PPR. The various accountable light power densities and number of surface trap states are considered to be directly realizing these spike-timing interval-dependent characteristics. The actual benefit of these characteristics is the dual temporal coding modes based on multiplicative operation using a ZTO/ZnO NP phototransistor realized via the active gate voltage modulation. The contrary tendency of the PPR index and temporal coding�a major biological neural coding�is well demonstrated by the potential of ZTO/ZnO NP phototransistors to be implemented in sensor networks for an artificial visual perception.

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Section: Resultsmentioning

confidence: 99%

Dual Light Temporal Coding Modes Enabled by Nanoparticle-Mediated Phototransistors via Gate Bias Modulation for Brain-Inspired Visual Perception

Zeng

Chu

Shih

et al. 2023

ACS Appl. Mater. Interfaces

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“…These harmonics are reduced to the greatest extent possible for better linearity and gain. Further, to analyze the distortion characteristics, 2 nd and 3 rd order harmonic distortions (HD2, HD3) and total harmonic distortion (THD) are measured from the approximate analytical expressions given as follows [37,38].…”

Section: Impact Of Itcs On Harmonic Distortionmentioning

confidence: 99%

“…Temperature-dependent SRH and TAT models used in the simulation are dominant at low gate voltages [37,42,43]. Hence the effect of temperature variations on I OF F is more.…”

Section: Impact Of Temperature On I Ds − V Gs Characteristicsmentioning

confidence: 99%

“…To address these concerns, researchers proposed various device structures such as double-gate, dual material gate, workfunction engineering, material engineering, stacked gate oxide, pocket doping, electrically doped (ED), dielectric pocket, and gate over source overlap, and extended source TFET [10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28]. In addition to the above issues, the reliability issues that arise as a result of ITCs developed at the Si-SiO 2 interface due to variations in process, stress, radiation, and the effect of hot carriers are also major concerns [32][33][34][35][36][37][38]. A higher electric field at the source-channel interface is required in TFET to reduce the tunneling barrier width, but this high transverse electric field results in the generation of interface traps (donor and acceptor) and thus the localized charges (both positive and negative).…”

Section: Introductionmentioning

confidence: 99%

“…Moreover, the device performance variation with temperature is also one of the causes of concern in nanoscale devices [37][38][39][40][41][42][43]. The device's on-chip performance is always influenced by its operating temperature.…”

Section: Introductionmentioning

confidence: 99%

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Impact of Interface Trap Charges and Temperature on the Performance of Extended Source Double Gate TFET

Dharmender

Nigam

Kumar

2022

Preprint

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In this work, we have investigated the reliability of the extended source double gate tunnel field-effect transistor (ESDG-TFET) by considering the effect of the fixed donor (positive) and acceptor (negative) interface trap charges (ITCs) at the silicon-SiO2 interface and temperature variations ranging from 300K to 480K, on the DC, analog/radio frequency (RF), linearity and harmonic distortion performance parameters. A comparative analysis has been performed between conventional stack gate oxide double gate TFET (SGO-DG-TFET) and ESDG-TFET with similar dimensions. Different performance metrics such as transfer characteristics, parasitic capacitances, gain-bandwidth product (GBP), unity gain frequency (fT), transit time, transconductance frequency product (TFP), and linearity distortion performance parameters such as 2nd and 3rd order transconductance coefficients (gm2, gm3), 2nd and 3rd order voltage intercept points (VIP2, VIP3), 3rd order input intercept point, intermodulation distortion parameters (IIP3, IMD3), and 1dB compression point have been investigated. Moreover, 2nd and 3rd order harmonic distortions (HD2, HD3) and total harmonic distortion (THD) are investigated using technology computer-aided design (TCAD) simulations. The Tables 2, 3 and 4 show that in terms of percentage variation, ESDG-TFET exhibits less variation as compared to SGO-DG-TFET, which indicates that the ESDG-TFET is more immune to ITCs and temperature variations. Thus, ESDG-TFET can be used for low power switching and analog/RF and high temperature applications.

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Quantum‐Engineered Devices Based on 2D Materials for Next‐Generation Information Processing and Storage

et al. 2022

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As an approximation to the quantum state of solids, the band theory, developed nearly seven decades ago, fostered the advance of modern integrated solid‐state electronics, one of the most successful technologies in the history of human civilization. Nonetheless, their rapidly growing energy consumption and accompanied environmental issues call for more energy‐efficient electronics and optoelectronics, which necessitate the exploration of more advanced quantum mechanical effects, such as band‐to‐band tunneling, spin–orbit coupling, spin–valley locking, and quantum entanglement. The emerging 2D layered materials, featured by their exotic electrical, magnetic, optical, and structural properties, provide a revolutionary low‐dimensional and manufacture‐friendly platform (and many more opportunities) to implement these quantum‐engineered devices, compared to the traditional electronic materials system. Here, the progress in quantum‐engineered devices is reviewed and the opportunities/challenges of exploiting 2D materials are analyzed to highlight their unique quantum properties that enable novel energy‐efficient devices, and useful insights to quantum device engineers and 2D‐material scientists are provided.

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Investigation of interface trap charges and temperature variation in heterostacked-TFET

Cited by 18 publications

References 41 publications

Dual Light Temporal Coding Modes Enabled by Nanoparticle-Mediated Phototransistors via Gate Bias Modulation for Brain-Inspired Visual Perception

Dual Light Temporal Coding Modes Enabled by Nanoparticle-Mediated Phototransistors via Gate Bias Modulation for Brain-Inspired Visual Perception

Impact of Interface Trap Charges and Temperature on the Performance of Extended Source Double Gate TFET

Quantum‐Engineered Devices Based on 2D Materials for Next‐Generation Information Processing and Storage

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