Investigation of electrically gate-all-around hexagonal nanowire FET (HexFET) architecture for 5 nm node logic and SRAM applications

Smith, J. A.; Ni, Kai; Ghosh, Ram Krishna; Xu, Jeff; Badaroglu, Mustafa; Chidambaram, P.R.; Datta, Suman

doi:10.1109/essderc.2017.8066623

Cited by 6 publications

(3 citation statements)

References 14 publications

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“…Therefore, significant resources have been spent on building high-performance integrated circuits in recent technology nodes. Unfortunately, it is expected that the device complication will get worse as new device structures such as Gate-All-Around FET (GAAFET) in Huang et al [2017], Smith et al [2017] or Tunneling FET in Krishnamohan et al [2008] are considered for the next primitive device elements in combination with complex local interconnects and multiple patterning technologies for dense routing.…”

Section: Introductionmentioning

confidence: 99%

A Custom IC Layout Generation Engine Based on Dynamic Templates and Grids

Shin¹,

Lee²,

Kim³

et al. 2022

Preprint

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This paper presents an automatic layout generation framework in advanced CMOS technologies. The framework extends the template-and-grid-based layout generation methodology with the following additional techniques applied to produce optimal layouts more effectively. First, layout templates and grids are dynamically created and adjusted during runtime to serve various structural, functional, and design requirements. Virtual instances support the dynamic template-and-grid-based layout generation process. The framework also implements various post-processing functions to handle process-specific requirements efficiently. The post-processing functions include cut/dummy pattern generation and multiple-patterning adjustment. The generator description capability is enhanced with circular grid indexing/slicing and conditional conversion operators. The layout generation framework is applied to various design examples and generates DRC/LVS clean layouts automatically in multiple CMOS technologies.

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Section: Introductionmentioning

confidence: 99%

A Custom IC Layout Generation Engine Based on Dynamic Templates and Grids

Shin¹,

Lee²,

Kim³

et al. 2022

Preprint

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“…Mais importante, o excelente acoplamento da porta com a região de canal nesses dispositivos permitiu o escalamento da largura do fin para valores próximos daqueles da altura do fin, dando origem à estrutura conhecida como nanofios transistores MOS (NanoWire transistor -NW) (COQUAND et al, 2012). Apresentando bom desempenho em aplicações digitais devido à forte imunidade a efeitos de canal curto, inclinação de sublimiar próxima do limite teórico (SAITO et al, 2002) e alto controle de cargas pela porta, tais dispositivos têm sido considerados, em muitos casos, como um dos mais promissores para futuros nós tecnológicos (BARRAUD et al, 2012;SMITH et al, 2017). Outra estrutura desenvolvida a partir da ideia do nanofio é o transistor de porta circundante (Gate-All-Around -GAA) (COLINGE et al, 1990), onde o material de porta envolve toda a região de canal do transistor, resultando em um maior número de interfaces entre o silício e o óxido de porta de para geração de canais de condução, aumentando ainda mais o controle das cargas pela porta (BANGSARUNTIP et al, 2009).…”

Section: Degunclassified

Efeitos da aplicação de técnicas de aprimoramento de desempenho em transistores SOI CMOS de tecnologias totalmente depletadas promissoras

Bergamaschi¹

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Agradeço primeiramente a Deus por guiar meu caminho e por me dar forças para ultrapassar todos os obstáculos da vida.Aos meus pais, Márcio e Maria Terezinha, e ao meu irmão, César, por estarem sempre ao meu lado para dar qualquer tipo de apoio necessário, me ajudando a atravessar as inseguranças e as dificuldades que surgem ao longo da vida, sempre buscando me fazer evoluir e crescer como pessoa e como profissional.

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“…A redução das dimensões da seção transversal da aleta de transistores de porta tripla e circundante para alguns nanômetros deu origem a uma nova geração de dispositivos de múltiplas portas, os quais foram denominados nanofios transistores MOS (NW -Nanowire Transistor) (BANGSARUNTIP et al, 2009;COQUAND et al, 2012aCOQUAND et al, , 2012b. Estudos demonstraram que nanofios transistores MOS apresentam alto controle eletrostático e, portanto, excelentes características elétricas para aplicações digitais, como memórias e microprocessadores (BARRAUD et al, 2012;PAN et al, 2015;SMITH et al, 2017). A investigação de nanofios transistores avançados, com comprimentos de canal da ordem de 20nm e largura da aleta de silício de até 5nm, mostrou correntes de estado desligado da ordem de 10 -11 A, inclinação de sublimiar próxima do limite teórico (~62mV/dec) e baixa influência do potencial no dreno sobre a tensão de limiar (~12mV/V), indicando-os como potenciais candidatos para a implementação de futuros nós tecnológicos (BARRAUD et al, 2012;COQUAND et al, 2012a;DESHPANDE et al, 2012;SMITH et al, 2017).…”

Section: Introductionunclassified

Avaliação da influência da evolução das tecnologias de fabricação de nanofios transistores MOS sobre suas características elétricas

Paz¹

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This work aims to study the influence of different fabrication technologies of inversion mode nanowires MOS transistors (NWs) through the evaluation and comparison of their electrical characteristics obtained from experimental measurements. Tridimensional numerical simulations are also used to allow the understanding of observed physical effects and to validate parameters extraction methods proposed in this work. Following the technological evolution of fabrication of NWs recently proposed, the influence of fin width, strain and stacking of nanowires is verified, mainly, over analog behavior and carriers' mobility. The comparisons performed in this work allow picking the technology that presents the best performance for each parameter analyzed. Several nanowires with fin width as narrow as 9.5nm and up to 10µm (quasi-planar) are analyzed. The fin width influence on the analog parameters is studied for n-and p-type non-stacked NWs with channel lengths of 10µm and 40nm. Effective mobility results are correlated to the harmonic distortion to explain linearity peaks behavior with temperature and fin width. Narrow transistors show improved linearity mainly due to higher intrinsic voltage gain. Back bias influence is studied in narrow NWs, where mobility varies due to carriers' density and inversion channel position along the fin. Strained and unstrained n-type NWs are compared using experimental results in the temperature range of 300 down to 10K, where mobility behavior is the major responsible for the analog parameters dependence on temperature. Uniaxial compressive strain obtained through SiGe in p-type nanowires shows to be beneficial for mobility, where improvements reach up to 68% for fin width of 20nm at room temperature. Strained vertically stacked p-type SOI nanowires with inner spacers and [110]-and [100]-oriented channels are studied as a function of both fin width and channel length. Procedures to extract the effective oxide thickness and fin width are adapted and validated through tridimensional numerical simulations. Overall effective mobility for stacked NWs is lower in comparison to nonstacked NWs due to small contribution from the top GAA level and threshold voltage mismatches, according to the investigation promoted by the proposed methodology to dissociate the low field mobility contributions from the top and bottom levels that compose the stacked structure.

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Investigation of electrically gate-all-around hexagonal nanowire FET (HexFET) architecture for 5 nm node logic and SRAM applications

Cited by 6 publications

References 14 publications

A Custom IC Layout Generation Engine Based on Dynamic Templates and Grids

A Custom IC Layout Generation Engine Based on Dynamic Templates and Grids

Efeitos da aplicação de técnicas de aprimoramento de desempenho em transistores SOI CMOS de tecnologias totalmente depletadas promissoras

Avaliação da influência da evolução das tecnologias de fabricação de nanofios transistores MOS sobre suas características elétricas

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