Investigation of device physics and modeling of semi-floating gate image sensor cell

Yao, Yao; Liu, Lei; Ye, Zhiyuan; Lin, Mengyan; Su, Zheng-Yuan; Jun, Wu; Wang, Pengfei

doi:10.1016/j.mee.2019.111111

Cited by 3 publications

(3 citation statements)

References 8 publications

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“…To further understand the round-sweep transfer characteristic curve shown in Figure 2a, the V BG -dependent carrier concentrations (Figure 2b) and the Fermi energies (Figure 2c) of the left and right components of WSe 2 channel are numerically calculated, and then the built-in voltage as a function of V BG (Figure 2d) is derived. The detailed computational procedure [42,43] and the fitting parameters are presented in Section S1 (Supporting Information). The turbostratic stacking is approximated for the floating gate multilayer graphene, and the density of states is proportional to the layer number of graphene (Equation S4 in Supporting Information).…”

Section: Resultsmentioning

confidence: 99%

Non‐Volatile and Gate‐Controlled Multistate Photovoltaic Response in WSe₂/h‐BN/Graphene Semi‐Floating Gate Field‐Effect Transistors

Fu,

Shi,

Cai

et al. 2024

Advanced Optical Materials

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Semi‐floating gate field‐effect transistors (SFG‐FETs) based on 2D materials have received much attention due to their unique optoelectronic characteristics, potential applications in near‐memory computing and constructing sensing‐memory‐processing units. Here, the non‐volatile and gate‐controlled multistate photovoltaic response of a WSe2/h‐BN/graphene SFG‐FET is investigated both in experimental and theoretical aspects. Due to the ambipolar carrier transport of WSe2 channel, both electrons and holes can be stored in the graphene floating gate layer, which results in two evident memory windows on the round sweep transfer characteristic curve. Different charge‐stored states of the SFG layer enable the channel to form a lateral junction that can be adjusted by the gate voltage, which leads to the gate‐controlled multistate photovoltaic response. A theoretical model is implemented to explain the memory and the multistate photovoltaic response behaviors in a quasi‐quantitative level. The relationship between the charge‐stored states in the SFG and the photo‐response, as well as its dependence on the gate voltage are systematically analyzed. These research results provide a reliable way for realizing high‐performance multi‐functional photodetectors based on SFG‐FETs and for thorough understanding the complicated optoelectronic behaviors of SFG‐FETs.

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Section: Resultsmentioning

confidence: 99%

Non‐Volatile and Gate‐Controlled Multistate Photovoltaic Response in WSe₂/h‐BN/Graphene Semi‐Floating Gate Field‐Effect Transistors

Fu,

Shi,

Cai

et al. 2024

Advanced Optical Materials

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“…FG RAM is different from the previous memory devices. The charge could be stored in a floating gate layer [24][25][26]118] . The schematic of the FG RAM devices is shown in Fig.…”

Section: Floating Gate Random-access Memorymentioning

confidence: 99%

A revew of in situ transmission electron microscopy study on the switching mechanism and packaging reliability in non-volatile memory

et al. 2021

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Non-volatile memory (NVM) devices with non-volatility and low power consumption properties are important in the data storage field. The switching mechanism and packaging reliability issues in NVMs are of great research interest. The switching process in NVM devices accompanied by the evolution of microstructure and composition is fast and subtle. Transmission electron microscopy (TEM) with high spatial resolution and versatile external fields is widely used in analyzing the evolution of morphology, structures and chemical compositions at atomic scale. The various external stimuli, such as thermal, electrical, mechanical, optical and magnetic fields, provide a platform to probe and engineer NVM devices inside TEM in real-time. Such advanced technologies make it possible for an in situ and interactive manipulation of NVM devices without sacrificing the resolution. This technology facilitates the exploration of the intrinsic structure-switching mechanism of NVMs and the reliability issues in the memory package. In this review, the evolution of the functional layers in NVM devices characterized by the advanced in situ TEM technology is introduced, with intermetallic compounds forming and degradation process investigated. The principles and challenges of TEM technology on NVM device study are also discussed.

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“…As a result, many recent applications that deploy FGTs are still not resorting to sub 70 nm transistors with sub 5 nm dielectric thicknesses. [28,29] In this work, a standard 65 nm CMOS process with 2 nm dielectric-thick MOSFETs is utilized to characterize our proposed CT cell, focusing on its main features like effective voltage range and retention time. After proper characterization, the fabricated CT cell was modeled in VerilogAMS and integrated with a memristor emulator adapted from ref.…”

Section: Introductionmentioning

confidence: 99%

A Memristive Cell with Long Retention Time in 65 nm CMOS Technology

Assaf

Savaria

Ali

et al. 2023

Adv Elect Materials

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of programmable devices are retention time, conductanceoperating voltage range, device dimensions, and robustness. [3] The memristor, which is considered the fourth circuit element, [4] is a good example of a programmable resistor. [5,6] Along with other resistive devices, memristors have been integrated into several domains such as: a) computing including in-memory computing, near-memory computing, and resistive computing with crossbar arrays, b) data storage including both passive and active types corresponding to long-term and short-term data retention times, respectively, and c) other domains such as logic-gate realizations and radio-frequency switches.However, due to challenges faced with memristor fabrication, these nano-devices are often replaced by emulating circuits fabricated using a standard CMOS process. [7] Although many memristor emulators have circuit responses close to that of the actual device, they still lack the potential to trap charges for long periods of time, a problem that is commonly solved using charge traps (CTs). A CT is a circuit branch designed to prolong the circuit's retention time, and in most designs, it is implemented using floating gate transistors (FGTs) which have been demonstrated in 1971. [8] FGTs were utilized in various applications that need non-volatile analog memories as in electrically erasable programmable read only memories (EEPROMs). [9] They have also become an integral part of analog computing engines that depend on crossbar arrays, replacing the tiny resistive devices in these structures. [10] Moreover, FGTs were used in programmable analog solvers like field programmable analog arrays (FPAAs), which add flexibility to analog-based circuit solutions. [11,12] Some CTs (an FGT trap, for example) can trap charges for long periods of time (up to 10 years). This characteristic is often referred to as retention time. The underlying CMOS process has a direct effect on this characteristic. Not only are CTs characterized by their retention times, but also by other features that contribute to giving each CT a unique identity. Some of these features which directly relate to FGTs are: a) the transistor dimensions, length and width, which affect the tunneled current and induce more parasitic capacitance in a cell; b) the dielectric thickness which has a direct effect on charge tunneling; c) the charging capacity, and d) the discharging

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Investigation of device physics and modeling of semi-floating gate image sensor cell

Cited by 3 publications

References 8 publications

Non‐Volatile and Gate‐Controlled Multistate Photovoltaic Response in WSe₂/h‐BN/Graphene Semi‐Floating Gate Field‐Effect Transistors

Non‐Volatile and Gate‐Controlled Multistate Photovoltaic Response in WSe₂/h‐BN/Graphene Semi‐Floating Gate Field‐Effect Transistors

A revew of in situ transmission electron microscopy study on the switching mechanism and packaging reliability in non-volatile memory

A Memristive Cell with Long Retention Time in 65 nm CMOS Technology

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Investigation of device physics and modeling of semi-floating gate image sensor cell

Cited by 3 publications

References 8 publications

Non‐Volatile and Gate‐Controlled Multistate Photovoltaic Response in WSe2/h‐BN/Graphene Semi‐Floating Gate Field‐Effect Transistors

Non‐Volatile and Gate‐Controlled Multistate Photovoltaic Response in WSe2/h‐BN/Graphene Semi‐Floating Gate Field‐Effect Transistors

A revew of in situ transmission electron microscopy study on the switching mechanism and packaging reliability in non-volatile memory

A Memristive Cell with Long Retention Time in 65 nm CMOS Technology

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Product

Resources

About

Non‐Volatile and Gate‐Controlled Multistate Photovoltaic Response in WSe₂/h‐BN/Graphene Semi‐Floating Gate Field‐Effect Transistors

Non‐Volatile and Gate‐Controlled Multistate Photovoltaic Response in WSe₂/h‐BN/Graphene Semi‐Floating Gate Field‐Effect Transistors