Investigation of Carbon Nanotube FET with Coaxial Geometry

Vimala, P.; L, Likith Krishna; Maheshwari, K. P.; Sharma, Shairy

doi:10.21272/jnep.12(5).05027

Cited by 8 publications

(5 citation statements)

References 11 publications

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“…Thus, the GAA CNTFET has the potential to be further miniaturized with a better performance. Another physical parameter that is found study in the literature is the dielectric materials [20,21]. The dielectric materials also play an important role to control the electrostatic charge at the gate.…”

Section: Designing the Cntfetmentioning

confidence: 99%

Optimized design of carbon nanotube field-effect transistor using Taguchi method for enhanced current ratio performance

Abdul Hadi,

Hussin,

Muhamad

et al. 2024

Phys. Scr.

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Presently, the integrated circuit (IC) industry grapples with obstacles in downsizing MOSFET technology further, hindered by its inherent physical constraints. Therefore, the substitution of silicon with carbon nanotubes (CNTs) holds promise for paving a novel path in semiconductor industries, driven by their diminutive dimensions and superior electrical properties. Hence, this project employed SILVACO ATLAS software in conjunction with the Taguchi method to refine a CNTFET design for optimal performance. In this work, response variables consists of on-current (Ion), current ratio (Ion/Ioff) and threshold voltage (Vth) are extracted. In this particular design, the Taguchi method was employed to ascertain the most effective combination of design parameters and materials to achieve optimal CNTFET performance, as assessed by the three key response variables. The design parameter and material that had been chosen were the diameter of carbon nanotube (Dcnt), dielectric material (K) and oxide thickness (tox). Each of the design parameters and material had three different values. For K, the values are 3.9 (SiO2), 25 (ZrO2) and 80 (TiO2). While for Dcnt and tox, the values are 4.0 nm, 6.0 nm, 8.0 nm and 2.0 nm, 4.0 nm, 6.0 nm respectively. According to the Taguchi optimization findings, the ideal combination of parameters comprises a CNT diameter of 4.0 nm, an oxide thickness of 2.0 nm, and the use of TiO2 (80) as the dielectric material. The ANOVA analysis underscores the significance of prioritizing optimization efforts towards the CNT diameter parameter. This is attributed to its substantial contribution, accounting for 93.55% of the variation in the Ion/Ioff value, surpassing the influence of dielectric materials and oxide thickness.

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Section: Designing the Cntfetmentioning

confidence: 99%

Optimized design of carbon nanotube field-effect transistor using Taguchi method for enhanced current ratio performance

Abdul Hadi,

Hussin,

Muhamad

et al. 2024

Phys. Scr.

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“…It should be noted that the electrical characteristics were obtained using diffusion equations to describe the ballistic transport of charge carriers [15][16][17][18][19][20] in FETs with 3D channels and contacts.…”

Section: -4mentioning

confidence: 99%

Electrical and Temperature Characteristics of Transistors with a Channel in the Form of a Carbon Nanotube

Buryk¹,

Martynenko²,

Odnodvorets³

et al. 2022

J. Nano- Electron. Phys.

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Carbon nanotubes (CNTs) are promising materials for the formation of field-effect transistors (FETs) due to their excellent electrical, thermal, mechanical and other properties. High productivity, low power consumption, minimization of the impact of short-channel effects, etc., are of significant practical interest primarily to coaxial CNTFETs. This paper presents the results of numerical simulation of coaxial gate-allaround (GAA) CNTFETs. The structure of GAA CNTFETs is designed using Silvaco TCAD tools and their electrical parameters are investigated. The drift diffusion model of transport, taking into account the Bohm quantum potential, demonstrates excellent characteristics for three-dimensional models, in particular, valid values are obtained for the threshold voltage Vt, subthreshold swing SS, switching current Ion, leakage current Ioff and Ion/Ioff coefficient. The influence of temperature on the specified electrical parameters at low bias voltages is studied and the typical character of temperature dependences for semiconductor devices is obtained. It is established that the values of the threshold voltage Vt and subthreshold swing SS decrease and increase, respectively, with increasing temperature from 250 to 500 K. Along with this, there is a slight decrease in the switching current by 1.6 % in a given temperature range at the source voltage VDD  -1.0 V. The thermal stability of coaxial structures of nanotransistors with a channel in the form of a single-walled CNT is evaluated by the temperature coefficients

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“…Different devices are proposed for reducing leakage current and power dissipation [1][2][3][4]. FinFET technology is one of most important technology for VLSI design [5][6][7][8].…”

Section: Introductionmentioning

confidence: 99%

Performance Enhancement of the Urdhva-Tiryagbhyam based Vedic Multiplier using FinFET

Vimala,

Hosmani

2024

J. Nano- Electron. Phys.

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The demand for quick and effective real-time DSP ("Digital Signal Processing") applications has increased as a result of rapidly developing technologies. One of the fundamental mathematical processes that any application needs is multiplication. There are many uses for the Vedic Multiplier in the broad fields of image processing and DSP, notably the several variations of the original Vedic Multiplier topologies that improve speed and performance. The aim of a paper is to design the Vedic multiplier in MOSFET and Fin-FET technology and reduce the power and time of the design. For reducing the delay and power three different technology of adder is designed which are "GDI", "Dual domino rail adder" and "Traditional adder". The GDI technology has a better performance like lower power, delay and number of transistors so that using the GDI technology is used as the logic to design as full adder half adder and AND gate. To design the 2-bit multiplier it required four AND gate and two half adders to obtain the partial product. Later by using the 2bit multiplier and 4-bit Ripple Carry Adder the 4-bit multiplier is mapped. Later using the 4-bit multiplier design the 8-bit multiplier is mapped. The proposed design is designed in MOSFET and FinFET technology as the result FinFET technology consume lower power and delay because of its lower leakage, higher drain current and higher performance. By using the FinFET technology overall performance will be 433.05 mW power and 0.981ns delay and MOSFET consumes 657.65 mW and 1.367 ns.

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Investigation of Carbon Nanotube FET with Coaxial Geometry

Cited by 8 publications

References 11 publications

Optimized design of carbon nanotube field-effect transistor using Taguchi method for enhanced current ratio performance

Optimized design of carbon nanotube field-effect transistor using Taguchi method for enhanced current ratio performance

Electrical and Temperature Characteristics of Transistors with a Channel in the Form of a Carbon Nanotube

Performance Enhancement of the Urdhva-Tiryagbhyam based Vedic Multiplier using FinFET

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