Investigating the TLB Behavior of High-end Scientific Applications on Commodity Microprocessors

McCurdy, Collin; Cox, Alan L.; Vetter, Jeff

doi:10.1109/ispass.2008.4510742

Cited by 43 publications

(30 citation statements)

References 18 publications

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“…Address translation, especially with virtualization and larger application working sets, is a primary source of system performance degradation [8,21]. In response, researchers have considered techniques to improve TLB structure, lookup, and placement [9,13].…”

Section: Prior Tlb Enhancement Techniquesmentioning

confidence: 99%

See 1 more Smart Citation

CoLT: Coalesced Large-Reach TLBs

Pham

Vaidyanathan

Jaleel

et al. 2012

2012 45th Annual IEEE/ACM International Symposium on Microarchitecture

154

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Section: Prior Tlb Enhancement Techniquesmentioning

confidence: 99%

“…Past work has shown that TLB misses degrade performance by 5% to 14% for even nominally-sized applications. This number worsens to 50% in virtualized environments or when the application's memory footprint increases [8,21].…”

Section: Introductionmentioning

confidence: 99%

CoLT: Coalesced Large-Reach TLBs

Pham

Vaidyanathan

Jaleel

et al. 2012

2012 45th Annual IEEE/ACM International Symposium on Microarchitecture

154

View full text Add to dashboard Cite

show abstract

“…The TLB behavior for scientific applications on commodity microprocessors was studied in [7]. Their work is similar in theme to ours.…”

Section: Related Workmentioning

confidence: 65%

An Analysis of HPC Benchmarks in Virtual Machine Environments

Tikotekar

Vallée

Naughton

et al. 2009

Euro-Par 2008 Workshops - Parallel Processing

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Abstract. Virtualization technology has been gaining acceptance in the scientific community due to its overall flexibility in running HPC applications. It has been reported that a specific class of applications is better suited to a particular type of virtualization scheme or implementation. For example, Xen has been shown to perform with little overhead for compute-bound applications. Such a study, although useful, does not allow us to generalize conclusions beyond the performance analysis of that application which is explicitly executed. An explanation of why the generalization described above is difficult, may be due to the versatility in applications, which leads to different overheads in virtual environments. For example, two similar applications may spend disproportionate amount of time in their respective library code when run in virtual environments. In this paper, we aim to study such potential causes by investigating the behavior and identifying patterns of various overheads for HPC benchmark applications. Based on the investigation of the overhead profiles for different benchmarks, we aim to address questions such as: Are the overhead profiles for a particular type of benchmarks (such as compute-bound) similar or are there grounds to conclude otherwise?

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“…Note that most SPEC CPU2006 benchmarks have small footprints, even with the reference input size. For larger applications, the performance improvement of superpage can be more significant [18]. …”

Section: Performancementioning

confidence: 99%

“…Recent work has shown that TLB misses can degrade performance by 5-14% for nominally-sized applications [3]. In the era of "big data", this number will degrade to 50% as application memory footprints increase [18]. The LLC is usually shared by all cores in today's multicore architectures.…”

Section: Introductionmentioning

confidence: 99%

A Swap-based Cache Set Index Scheme to Leverage both Superpage and Page Coloring Optimizations

Cui

Chen

Bao

et al. 2014

Proceedings of the 51st Annual Design Automation Conference

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We propose a novel cache set index scheme called SWAP (swap-based cache set index). SWAP introduces a pseudophysical address space that is used by the operating system. The real physical address used for cache and main memory access is obtained by simply swapping some of superpage number bits with cache set index bits from the pseudo-physical address. By adding a level of indirection to the physical memory management, we simultaneously support both page coloring and superpage optimizations. These work together to improve TLB and shared LLC performance with negligible cost. Our results show that SWAP can improve performance by an average of 15.1% (by up to 25.2%) compared to 7.34% and 8.26% for superpage and page coloring, respectively.

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Investigating the TLB Behavior of High-end Scientific Applications on Commodity Microprocessors

Cited by 43 publications

References 18 publications

CoLT: Coalesced Large-Reach TLBs

CoLT: Coalesced Large-Reach TLBs

An Analysis of HPC Benchmarks in Virtual Machine Environments

A Swap-based Cache Set Index Scheme to Leverage both Superpage and Page Coloring Optimizations

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