Investigating hardware acceleration for simulation of CFD quantum circuits

Abstract

Among the many computational models for quantum computing, the Quantum Circuit Model is the most well-known and used model for interacting with current quantum hardware. The practical implementation of quantum computers is a very active research field. Despite this progress, access to physical quantum computers remains relatively limited. Furthermore, the existing machines are susceptible to random errors due to quantum decoherence, as well as being limited in number of qubits, connectivity and built-in error correction. Simulation on classical hardware is therefore essential to allow quantum algorithm researchers to test and validate new algorithms in a simulated-error environment. Computing systems are becoming increasingly heterogeneous, using a variety of hardware accelerators to speed up computational tasks. One such type of accelerators, Field Programmable Gate Arrays (FPGAs), are reconfigurable circuits that can be programmed using standardized high-level programming models such as OpenCL and SYCL. FPGAs allow to create specialized highly-parallel circuits capable of mimicking the quantum parallelism properties of quantum gates, in particular for the class of quantum algorithms where many different computations can be performed concurrently or as part of a deep pipeline. They also benefit from very high internal memory bandwidth. This paper focuses on the analysis of quantum algorithms for applications in computational fluid dynamics. In this work we introduce novel quantum-circuit implementations of model lattice-based formulations for fluid dynamics, specifically the D1Q3 model using quantum computational basis encoding, as well as, efficient simulation of the circuits using FPGAs. This work forms a step toward quantum circuit formulation of the Lattice Boltzmann Method (LBM). For the quantum circuits implementing the nonlinear equilibrium distribution function in the D1Q3 lattice model, it is shown how circuit transformations can be introduced that facilitate the efficient simulation of the circuits on FPGAs, exploiting their fine-grained parallelism. We show that these transformations allow us to exploit more parallelism on the FPGA and improve memory locality. Preliminary results show that for this class of circuits the introduced transformations improve circuit execution time. We show that FPGA simulation of the reduced circuits results in more than 3× improvement in performance per Watt compared to the CPU simulation. We also present results from evaluating the same kernels on a GPU.

Coupled cluster theory on modern heterogeneous supercomputers

“…The field of quantum chemistry and general electronic structure theory has witnessed productive research efforts in these directions, with researchers employing clever computational simplifications within new theoretical frameworks and developing new approaches that can effectively scale computations to larger problem sizes, improving the accuracy and efficiency of simulations. These developments have been well-documented in the literature ( Häser, 1993 ; Ishikawa and Kuwata, 2012 ; Monari et al, 2013 ; Helmich and Hättig, 2014 ; Díaz-Tinoco et al, 2016 ; Gyevi-Nagy et al, 2019 ; Mester et al, 2019 ; Nagy and Kállay, 2019 ; Ballesteros et al, 2021 ; Datta and Gordon, 2021 ; Gyevi-Nagy et al, 2021 ; Szabó et al, 2021 ; Abyar and Novak, 2022 ; Paudics et al, 2022 ; Semidalas and Martin, 2022 ).…”

“…Thus, calculations based on theories such as Density Functional Theory can benefit from this type of parallelization. Recently, fine-grained parallelism has been used to accelerate simulations of quantum circuits on Field Programmable Gate Arrays (FPGAs) (Moawad et al, 2022).…”

Floating-Point Arithmetic with Consistent Rounding on a Quantum Computer

“…An early work related to quantum circuits for floating-point arithmetic involved the complexity analysis of floating-point addition and multiplication by Häner and coworkers [8], which showed the significant challenges involved in terms of circuit complexity for IEEE-754 type precision. This motivated the present author to introduce floating-point formats for quantum algorithms with a reduced precision [12,16,17], such that the required number of qubits and the circuit complexity remain within limits of near-future quantum computers with an increased level of fault tolerance as compared to NISQ-era hardware.…”

Efficient and Fail-Safe Collisionless Quantum Boltzmann Method

“…Due to the high costs of quantum state preparation and the chance of measurement errors this 'stop-and-go' strategy is hardly usable in practice. Other algorithms have managed to create a unitary collision operator, but have not yet been able to combine this with a streaming step into one start-to-end algorithm [MVS22;Ste23].…”