2014
DOI: 10.1039/c3nr06904d
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Inverted process for graphene integrated circuits fabrication

Abstract: CMOS compatible 200 mm two-layer-routing technology is employed to fabricate graphene field-effect transistors (GFETs) and monolithic graphene ICs. The process is inverse to traditional Si technology. Passive elements are fabricated in the first metal layer and GFETs are formed with buried gate/source/drain in the second metal layer. Gate dielectric of 3.1 nm in equivalent oxide thickness (EOT) is employed. 500 nm-gate-length GFETs feature a yield of 80% and fT/fmax = 17 GHz/15.2 GHz RF performance. A high-per… Show more

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Cited by 14 publications
(9 citation statements)
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“…Combining its ultra-high electron mobility, tunable electronic transport polarity and ultrastrong intrinsic strength, graphene functions as a promising candidate for solid electronic13141516, flexible electronic171819, and sensing20212223. Graphene has wide applications for future high frequency electronics because of its ultrahigh carrier mobility and saturation velocity8.…”
mentioning
confidence: 99%
“…Combining its ultra-high electron mobility, tunable electronic transport polarity and ultrastrong intrinsic strength, graphene functions as a promising candidate for solid electronic13141516, flexible electronic171819, and sensing20212223. Graphene has wide applications for future high frequency electronics because of its ultrahigh carrier mobility and saturation velocity8.…”
mentioning
confidence: 99%
“…However, even though the cutoff frequency ( f T ) of graphene field-effect transistors (GFETs) exceed Si transistors 3 4 , the maximum oscillation frequency ( f max ), as the most relevant metric to circuit performance, seriously lags behind. Promising circuit applications are limited in passive circuits 5 6 7 8 9 . Typical f max values are one order of magnitude lower than f T 3 10 11 12 13 .…”
mentioning
confidence: 99%
“…In this work, the modern CMOS back-end-of-line (BEOL) technology has been employed to fabricate deep-submicron GFETs. GFETs with gate lengths ranging from 100 nm to 400 nm have been fabricated on 200 mm wafers by recently reported passive-first-active-last inverted process 8 9 20 . In particular, buried gates with depth-to-width ratio up to six folds were achieved for the purpose of lowering the gate resistance.…”
mentioning
confidence: 99%
“…Poineering works on graphene circuits have led to the demonstration of frequency doublers 10 11 12 , ambipolor mixers 13 and modulators 14 15 , in which graphene’s unique property of electron and hole symmetry is utilized. By superimposing an sinusoidal signal on the minimum conductance point (Dirac point), the electron or the hole branches, the frequency and phase of the output signal could be modulated.…”
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confidence: 99%
“…On the other hand, graphene’s IC process has witnessed substantial improvements 12 19 22 . Both Han et al and the authors’ group have proposed the multi-layer-routing inverted process for graphene integration, which serves as the foundation for future novel graphene circuit architectures 12 19 22 . The inverted process utilizes CMOS BEOL processes to fabricate circuit and device structures, followed by CVD graphene transfer at the back end of the flow.…”
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confidence: 99%