Inverse lithography technology (ILT): keep the balance between SRAF and MRC at 45 and 32 nm

Pang, Liang; Liu, Yong; Dam, Thuc; Mihić, Krešimir; Cecil, Thomas; Abrams, Dan

doi:10.1117/12.754568

Cited by 23 publications

(19 citation statements)

References 14 publications

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“…ILT model based SRAF has demonstrated its significantly better performance in process window (PW) over conventional OPC approaches [2,4,5] . With increased performance with SRAF insertion, the mask write time is increased accordingly.…”

Section: Local CD Aware Selective Srafmentioning

confidence: 99%

“…It enables computation of optimum mask patterns to minimize deviations of images from their targets not only at nominal but also over a range of process variations, such as dose, defocus, and mask CD errors. Masks computed through the use of ILT are known to provide significantly better lithographic performance than conventional rule-based and even model-based OPC [3][4][5][6] .…”

Section: Introductionmentioning

confidence: 99%

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Affordable and process window increasing full chip ILT masks

et al. 2010

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To enable Inverse Lithography Technology (ILT) for production as one of the leading candidates for low-k 1 lithography at 32nm and below, one major task to overcome is mask manufacturability including mask data fracturing, MRC constraints, writing time, and inspection. In prior publications [1,2] , it has been shown that the Inverse Synthesizer (IS™) produces ILT full chip mask of contact layer with comparable mask write time with conventional OPC while maintaining the significant litho gains of ILT mask.To fully integrate ILT masks into production for all layers including line and space layers such as poly layer, a number of areas were investigated to further reduce ILT mask complexity and total e-beam shot count. These areas include flexible controls of SRAF placements with respect to local feature sizes, improved Manhattan algorithm, topology based variable Manhattan segmentation, jog alignment and mask data fracture optimization. The impact of these approaches on e-beam shot count and lithography performance of ILT masks is presented in the paper.

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Section: Local CD Aware Selective Srafmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Affordable and process window increasing full chip ILT masks

et al. 2010

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“…6,7 To put ILT into practice, various methods have been proposed by academic as well as industrial communities on mask manufacturing rule constraints, 8,9 pattern grouping strategy to accelerate computing, 10 GPU-based hardware accelerated techniques, 11 and mathematical solution methods for the inverse problem. 4,5 In this paper, we focus on improvement of mathematical solution methods, where the computational efficiency is one of the most noteworthy issues. Currently, as critical dimension (CD) shrinks, the pattern density of integrated circuits gets much denser and lithographic process variations, such as lens-wafer defocus and exposure dose variation, become more pronounced.…”

Section: Introductionmentioning

confidence: 99%

“…[1][2][3] Inverse lithography technology (ILT), 4,5 as an active approach of RETs, is considered as an effective and economically viable way to meet various challenges in current and future technology nodes. 6,7 To put ILT into practice, various methods have been proposed by academic as well as industrial communities on mask manufacturing rule constraints, 8,9 pattern grouping strategy to accelerate computing, 10 GPU-based hardware accelerated techniques, 11 and mathematical solution methods for the inverse problem.…”

Section: Introductionmentioning

confidence: 99%

Cascadic multigrid algorithm for robust inverse mask synthesis in optical lithography

Lam

Wei

et al. 2014

J. Micro/Nanolith. MEMS MOEMS

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Abstract. Robust inverse mask synthesis is computationally intensive, and its turnaround time continues to rise hand-in-hand with the ever-shrinking integrated circuit feature size. We report the development of a cascadic multigrid (CMG) algorithm for robust inverse mask synthesis, which starts from a relatively coarse mask grid and refines it iteratively in stages, so as to achieve significant speedup without compromising numerical accuracy. Since the CMG algorithm entails frequent changes of the computational grid size, we need to intentionally introduce an analytical circle-sampling technique for modeling the forward lithography imaging and employ an edge distance error as metric to guide mask synthesis. These two techniques work nicely with variable grid sizes and are well suited for our CMG algorithm. As a result, our algorithm achieves more than four times speedup over conventional methods that synthesize a mask on a fixed fine grid. Numerical results are presented to demonstrate the validity and efficiency of the proposed method. © The Authors. Published by SPIE under a Creative Commons Attribution 3.0 Unported License. Distribution or reproduction of this work in whole or in part requires full attribution of the original publication, including its DOI.

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“…Various computation techniques have been proposed to deal with this inverse problem in the literature, such as the level-set method, [5][6][7][8] the discrete cosine transform (DCT)-based method, 9 and the gradient-based method. [10][11][12][13][14][15] The level-set method treats a mask as a sophisticated continuum, [5][6][7][8] and consequently, the boundary of the mask is iteratively evolved according to an optimization algorithm. The DCT-based method transforms a mask to the frequency space using a two-dimensional DCT.…”

Section: Introductionmentioning

confidence: 99%

Mask-filtering-based inverse lithography

Xia

Liu

2013

J. Micro/Nanolith. MEMS MOEMS

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Abstract. We propose a new regularization framework for inverse lithography that regularizes masks directly by applying a mask filtering technique to improve computational efficiency and to enhance mask manufacturability. This technique is different from the conventional regularization method that regularizes a mask by incorporating various penalty functions to the cost function. We design a specific mask filter for this purpose. Moreover, we introduce a metric called edge distance error (EDE) to guide mask synthesis and establish the correlation between pattern error and edge placement error (EPE) via EDE. We prove that EDE has the same dimension as EPE and has a continuous expression as pattern error. Simulation results demonstrating the validity and efficiency of the proposed method are presented. © The Authors. Published by SPIE under a Creative Commons Attribution 3.0 Unported License. Distribution or reproduction of this work in whole or in part requires full attribution of the original publication, including its DOI.

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Inverse lithography technology (ILT): keep the balance between SRAF and MRC at 45 and 32 nm

Cited by 23 publications

References 14 publications

Affordable and process window increasing full chip ILT masks

Affordable and process window increasing full chip ILT masks

Cascadic multigrid algorithm for robust inverse mask synthesis in optical lithography

Mask-filtering-based inverse lithography

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