8th International Symposium on Quality Electronic Design (ISQED'07) 2007
DOI: 10.1109/isqed.2007.94
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InVerS: An Incremental Verification System with Circuit Similarity Metrics and Error Visualization

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Cited by 6 publications
(1 citation statement)
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“…As in [9], we refine simulation using counterexamples found by failed equivalence checks, so as to reduces additional failed checks. We also minimize the verification time due to equivalence checking by considering only the portions of logic that contributes to the don't-cares used in the transformation.…”
Section: Efficient Subcircuit Verificationmentioning
confidence: 99%
“…As in [9], we refine simulation using counterexamples found by failed equivalence checks, so as to reduces additional failed checks. We also minimize the verification time due to equivalence checking by considering only the portions of logic that contributes to the don't-cares used in the transformation.…”
Section: Efficient Subcircuit Verificationmentioning
confidence: 99%