Introduction of Non-Volatile Computing In Memory (nvCIM) by 3D NAND Flash for Inference Accelerator of Deep Neural Network (DNN) and the Read Disturb Reliability Evaluation : (Invited Paper)

Lue, Hang-Ting; Hsu, Po-Kai; Wang, Keh-Chung; Lu, Chih‐Yuan

doi:10.1109/irps45951.2020.9128340

Cited by 5 publications

(3 citation statements)

References 3 publications

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“…Read disturb as well as program disturb can change the conductance of a synaptic device, reducing its accuracy. When implementing a synapse array with a NAND-type array, a pass voltage must be applied to de-selected cells of the same string during the inference operation, causing a read disturb ( Figure 10 a) [ 39 , 40 , 41 , 42 , 43 , 44 , 45 , 46 , 47 , 48 , 49 ]. However, in the proposed structure, there is little risk of a read disturb because there is no need to apply pass voltage to the word lines of de-selected cells ( Figure 10 b).…”

Section: Resultsmentioning

confidence: 99%

3D AND-Type Stacked Array for Neuromorphic Systems

et al. 2020

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NOR/AND flash memory was studied in neuromorphic systems to perform vector-by-matrix multiplication (VMM) by summing the current. Because the size of NOR/AND cells exceeds those of other memristor synaptic devices, we proposed a 3D AND-type stacked array to reduce the cell size. Through a tilted implantation method, the conformal sources and drains of each cell could be formed, with confirmation by a technology computer aided design (TCAD) simulation. In addition, the cell-to-cell variation due to the etch slope could be eliminated by controlling the deposition thickness of the cells. The suggested array can be beneficial in simple program/inhibit schemes given its use of Fowler–Nordheim (FN) tunneling because the drain lines and source lines are parallel. Therefore, the conductance of each synaptic device can be updated at low power level.

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Section: Resultsmentioning

confidence: 99%

3D AND-Type Stacked Array for Neuromorphic Systems

et al. 2020

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“…The second step is to compute inside Next and last step is to go on top of the memory hierarchy by computing directly in the SCM, where massive data storage and large vectors are available. 3D NAND Flash memory computing has been developed by [7] to improve deep neural networks power consumption. Indeed, the Flash memory is used to store the constant weights of the network.…”

Section: Related Workmentioning

confidence: 99%

“…Indeed, such solutions bring computation directly into the memory circuit, avoiding a large part of the data exchange with the CPU. Numerous IMC/NMC solutions have been proposed so far on the different levels of the memory hierarchy, from cache memory with Computing SRAM (C-SRAM) solutions [3], [4], primary memory with Computing DRAM (C-DRAM) [5], [6] and finally to storage class memory (SCM) [7]- [9] with Computing SCM (C-SCM) based on different technologies (Flash, PCM, MRAM, RRAM). All these solutions take advantage of the large memory array organisation to compute operations on very large vectors, close to the Single Instruction Multiple Data (SIMD) computation concept.…”

Section: Introductionmentioning

confidence: 99%

Storage Class Memory with Computing Row Buffer: A Design Space Exploration

Egloff

Noël

Kooli

et al. 2021

2021 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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Today computing centric von Neumann architectures face strong limitations in the data-intensive context of numerous applications, such as deep learning. One of these limitations corresponds to the well known von Neumann bottleneck. To overcome this bottleneck, the concepts of In-Memory Computing (IMC) and Near-Memory Computing (NMC) have been proposed. IMC solutions based on volatile memories, such as SRAM and DRAM, with nearly infinite endurance, solve only partially the data transfer problem from the Storage Class Memory (SCM). Computing in SCM is extremely limited by the intrinsic poor endurance of the Non-Volatile Memory (NVM) technologies.In this paper, we propose to take the best of both solutions, by introducing a Computing Row Buffer (C-RB), using a Computing SRAM (C-SRAM) model, in place of the standard Row Buffer (RB) in the SCM. The principle is to keep operations on large vectors in the C-RB of the SCM, minimizing data movement to and from the CPU, thus drastically reducing energy consumption of the overall system. To evaluate the proposed architecture, we use an instruction accurate platform based on Intel Pin software. Pin instruments run time binaries in order to get applications' full memory traces of our solution. We achieve energy reduction up to 7.9x on average and up to 45x for the best case and speedup up to 3.8x on average and up to 13x for the best case, and a reduction of write accesses in the SCM up to 18%, compared to SIMD 512-bit architecture.

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