Introducing hierarchy-awareness in replacement and bypass algorithms for last-level caches

Chaudhuri, Mainak; Gaur, Jayesh; Bashyam, Nithiyanandan; Subramoney, Sreenivas; Nuzman, Joseph

doi:10.1145/2370816.2370860

Cited by 53 publications

(49 citation statements)

References 24 publications

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“…In general, the main body of the cache bypassing techniques is to determine which block should be bypassed or not. For example, a reuse distance can be a key measure to determine whether to bypass or not [4,5,6,7]. Some other works consider reuse counts for making a decision in cache bypassing [8,9,10,11].…”

Section: Related Workmentioning

confidence: 99%

A DVFS-aware cache bypassing technique for multiple clock domain mobile SoCs

Kong

Lee

2017

IEICE Electron. Express

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Multiple clock domains mobile SoCs typically adopt dynamic voltage and frequency scaling (DVFS) for flexible power/energy management. However, adoption of system-level cache under DVFS-enabled CPU may incur abnormal cache hierarchy (i.e., a delay reversal between the highlevel and low-level caches). It may lead to performance-and energyinefficiency due to slower data delivery and meaningless accesses to intermediate levels of caches. To resolve this problem, we propose a DVFS-aware cache bypassing technique. Our technique profiles latencies of the various levels of the caches. Based on the profiled information, our technique adaptively bypasses intermediate levels of caches in the case of abnormal cache hierarchy and applies power-gating to that cache memory for better energy efficiency. According to our evaluation, our technique reduces L2 and system-level cache energy consumption by up to 14.5% while improving performance by up to 0.13% compared to the baseline.

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Section: Related Workmentioning

confidence: 99%

A DVFS-aware cache bypassing technique for multiple clock domain mobile SoCs

Kong

Lee

2017

IEICE Electron. Express

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“…When a miss is encountered here, the resulting overhead can be higher compared to other cache levels. Many works [2,3,5,6,8,9] have emerged in recent times which strive to improve the performance at LLC.…”

Section: Related Workmentioning

confidence: 99%

“…A method which was proposed by Mainak Chaudhuri et al [8] discusses on how the activities occurring in the inner levels of the cache can be used to make replacement decisions in the LLC. Here activities refer to the pattern of hits and misses encountered.…”

Section: Related Workmentioning

confidence: 99%

Sharing and Hit based Prioritizing Replacement Algorithm for Multi-Threaded Applications

Muthukumar¹,

K²

2014

IJCA

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Cache replacement techniques like LRU, MRU etc. that are currently being deployed across multi-core architecture platforms, try to classify elements purely based on the number of hits they receive during their stay in the cache. In multithreaded applications data can be shared by multiple threads (which might run on the same core or across different cores). Such data needs to be given more priority when compared to private data because miss on those data items may stall the functioning of multiple threads resulting in performance bottleneck. Since the traditional algorithms mentioned above do not possess this additional capability, they might lead to sub-optimal performance for most of the current multithreaded applications. To address this limitation, our paper proposes a Sharing and Hit Based Prioritizing (SHP) replacement strategy that takes the sharing status of the data elements into consideration while making replacement decisions. Every cache element is associated with a "Sharing Degree" which indicates the extent to which the element is shared based on the number of threads that try to access that element. There are four degrees of sharing namely -Not shared (or private), lightly shared, heavily shared and very heavily shared. Combining the sharing degree along with the number of hits received by the element, we embark on a priority based on which the replacement decisions are made. Evaluation results obtained using multi-threaded workloads derived from the PARSEC benchmark suite shows an average improvement of 4% to 5% in the overall hit rate when compared to LRU algorithm. General TermsMulti-Core Architecture, Cache Memory, Multi-Threaded Applications.

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“…The effect of inter-thread interference due to sharing has been extensively studied in small scale multi-core contexts [4,3,12,6,7,8,1,5,9,11,2]. However, with advancement in process technology, processors are evolving towards packaging more cores on a chip.…”

Section: Introductionmentioning

confidence: 99%

Discrete Cache Insertion Policies for Shared Last Level Cache Management on Large Multicores

Sridharan

Seznec

2016

2016 IEEE International Parallel and Distributed Processing Symposium (IPDPS)

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Abstract:Multi-core processors employ shared Last Level Caches (LLC). This trend will continue in the future with large multi-core processors (16 cores and beyond) as well. At the same time, the associativity of this LLC tends to remain in the order of sixteen. Consequently, with large multicore processors, the number of cores that share the LLC becomes larger than the associativity of the cache itself. LLC management policies have been extensively studied for small scale multi-cores (4 to 8 cores) and associativity degree in the 16 range. However, the impact of LLC management on large multi-cores is essentially unknown, in particular when the associativity degree is smaller than the number of cores. In this study, we introduce Adaptive Discrete and deprioritized Application PrioriTization (ADAPT), an LLC management policy addressing the large multi-cores where the LLC associativity degree is smaller than the number of cores. ADAPT builds on the use of the Footprint-number metric. Footprint-number is defined as the number of unique accesses (block addresses) that an application generates to a cache set in an interval of time. We propose a monitoring mechanism that dynamically samples cache sets to estimate the Footprint-number of applications and classifies them into discrete (distinct and more than two) priority buckets. The cache replacement policy leverages this classification and assigns priorities to cache lines of applications during cache replacement operations. Footprint-number is computed periodically to account the dynamic changes in applications? behavior. We further find that deprioritizing certain applications during cache replacement is beneficial to the overall performance. We evaluate our proposal on 16, 20 and 24-core multi-programmed workloads and discuss other aspects in detail.

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Introducing hierarchy-awareness in replacement and bypass algorithms for last-level caches

Cited by 53 publications

References 24 publications

A DVFS-aware cache bypassing technique for multiple clock domain mobile SoCs

A DVFS-aware cache bypassing technique for multiple clock domain mobile SoCs

Sharing and Hit based Prioritizing Replacement Algorithm for Multi-Threaded Applications

Discrete Cache Insertion Policies for Shared Last Level Cache Management on Large Multicores

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