Intrinsic dielectric stack reliability of a high performance bulk planar 20nm replacement gate high-k metal gate technology and comparison to 28nm gate first high-k metal gate process

McMahon, William E.; Tian, C.; Uppal, S.; Kothari, H.; Jin, Moo-Nyun; LaRosa, G.; Nigam, T.; Kerber, A.; Linder, B.; Cartier, E.; Lai, W.; Liu, Y.; Ramachandran, R.; Kwon, U.; Parameshwaran, B.; Krishnan, Siddarth; Narayanan, V.

doi:10.1109/irps.2013.6532016

Cited by 11 publications

(7 citation statements)

References 4 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Measurement Delay Impact Fraction remaining (FR) methodology was reported to simplify AC PBTI/NBTI modeling using no-interrupt DC stress followed by long term recovery based on the observation that AC PBTI is frequency independent in certain regime [5,6,9]. AC/DC degradation ratio is calculated by normalizing ΔV t at any t rec to ΔV t at the beginning of test (e.g.…”

Section: Discussion Of Fraction Remaining Methodology Andmentioning

confidence: 99%

See 1 more Smart Citation

Process dependence of AC/DC PBTI in HKMG n-MOSFETs

Liu

Rosa

Tian

et al. 2014

2014 IEEE International Reliability Physics Symposium

Self Cite

View full text Add to dashboard Cite

It is well known that n-MOSFET aging under AC and DC Positive Bias Temperature Instability (PBTI) is strongly dependent on the adopted HK stack processes. In this work it is reported, for the first time, a detailed analysis of the nature of the PBTI degradation and recovery under DC and AC conditions by a novel stress and test methodology. Our observations over two HK processes (A & B) support the PBTI physical picture of two uncorrelated independent contributions to the PBTI damage. Namely, electron trap activation in preexisting (before stress) process induced traps as well as electron traps generation in the HK bulk oxide. It is shown that the relative role of these two components to PBTI aging is strongly process dependent and fully explains the observed DC vs. AC PBTI process sensitivity. This finding challenges the generally expected dependence of AC/DC PBTI V t shift ratio as function of AC pulse duty cycle. The root cause of such a striking AC and DC PBTI aging differences in these two processes and its implication to technology qualification are discussed in details.

show abstract

Section: Discussion Of Fraction Remaining Methodology Andmentioning

confidence: 99%

“…The n-MOSFETs used in this study were fabricated using either Process-A or Process-B in a recent HKMG technology [9]. Fig.…”

Section: Methodsmentioning

confidence: 99%

Process dependence of AC/DC PBTI in HKMG n-MOSFETs

Liu

Rosa

Tian

et al. 2014

2014 IEEE International Reliability Physics Symposium

Self Cite

View full text Add to dashboard Cite

show abstract

“…1 that NBTI has emerged as a crucial p-MOSFET reliability issue since 90 nm technology node, when Silicon Oxynitride (SiON) replaced Silicon Dioxide (SiO 2 ) as the gate insulator [1,2]. NBTI remains as an important issue even today for planar MOSFETs and FinFETs having state-of-the-art High-K Metal Gate (HKMG) gate stacks [3,4]. Over the years, different physical mechanisms have been proposed to explain buildup of positive charges in the gate insulator during NBTI stress and were recently reviewed [5].…”

Section: Introductionmentioning

confidence: 99%

“…Mutually uncoupled ΔN IT and ΔN HT (and also ΔN OT for certain situations) mechanisms can explain different gate insulator process dependent NBTI data [5,[33][34][35], and is discussed later in Chap. 4.…”

Section: Introductionmentioning

confidence: 99%

“…1, the relative magnitude of NBTI and PBTI degradation respectively in p-and n-channel HKMG MOSFETs stressed under identical oxide field (E OX ) and temperature (T) depends on the gate insulator process and is industry specific [3,4]. Although NBTI results in trap generation and trapping in the IL layer while PBTI degrades the High-K layer, they demonstrate very similar behavior listed as follows, when measured by using Ultra-Fast Measure-Stress-Measure (UF-MSM) technique, refer to Chap.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Physical Mechanism of BTI Degradation—Direct Estimation of Trap Generation and Trapping

Mukhopadhyay

Mahapatra

2015

Fundamentals of Bias Temperature Instability in MOS Transistors

View full text Add to dashboard Cite

In this chapter, direct characterization techniques have been used to access the trap generation and trapping subcomponents of BTI degradation in HKMG MOSFETs having different gate stack processes. Generation of new traps is estimated using DCIV for NBTI stress and both DCIV and SILC for PBTI stress respectively in p-and n-channel MOSFETs. Flicker noise is used to estimate the density of process related pre-existing gate insulator traps responsible for hole and electron trapping respectively during NBTI and PBTI stress. The spatial and energetic locations of generated traps for NBTI and PBTI stress are identified. The time, bias, and temperature dependencies of trap generation obtained using the DCIV technique are compared between NBTI and PBTI stress, while these parameters obtained using DCIV and SILC techniques are compared for PBTI stress. The relative dominance of trap generation and trapping on NBTI and PBTI threshold voltage degradation is estimated for different gate insulator processes. IntroductionFrom a practical point of view of technology qualification, it is important to know the magnitude of Bias Temperature Instability (BTI) at end-of-life of devices and hence of circuits and products under normal use condition. Estimation of Negative BTI (NBTI) and Positive BTI (PBTI) respectively in p-and n-channel Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) is usually done by stressing the devices at higher than normal gate bias (V G = V G-STR ) and measuring the resulting device parametric degradation with minimal impact of recovery artifacts. Different "recovery-free" measurement techniques have been discussed in Chap. 2. As mentioned before, stress tests are usually performed for few hours or

show abstract

Modeling of DC and AC NBTI Degradation and Recovery for SiON and HKMG MOSFETs

Goel

Mahapatra

2015

Fundamentals of Bias Temperature Instability in MOS Transistors

View full text Add to dashboard Cite

Intrinsic dielectric stack reliability of a high performance bulk planar 20nm replacement gate high-k metal gate technology and comparison to 28nm gate first high-k metal gate process

Cited by 11 publications

References 4 publications

Process dependence of AC/DC PBTI in HKMG n-MOSFETs

Process dependence of AC/DC PBTI in HKMG n-MOSFETs

Physical Mechanism of BTI Degradation—Direct Estimation of Trap Generation and Trapping

Modeling of DC and AC NBTI Degradation and Recovery for SiON and HKMG MOSFETs

Contact Info

Product

Resources

About