Intralevel Hybrid Resist Process For The Fabrication Of Metal Oxide Semiconductor Devices With Submicron Gate Lengths

Holbert, J. N.; Seese, P. A.; Gonzales, A. J.; Walker, Casey

doi:10.1117/12.7973079

Opt. Eng

1983

DOI: 10.1117/12.7973079

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Intralevel Hybrid Resist Process For The Fabrication Of Metal Oxide Semiconductor Devices With Submicron Gate Lengths

J. N. Holbert

P. A. Seese

A. J. Gonzales

et al.

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Intralevel Hybrid Resist Process For The Fabrication Of Metal Oxide Semiconductor Devices With Submicron Gate Lengths

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