Interrupt handling for out-of-order execution processors

Torng, H. C.; Day, M. N.

doi:10.1109/12.192223

Cited by 17 publications

(7 citation statements)

References 9 publications

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“…The restart mechanism illustrated in Fig. 5 is that suggested by [10]. In this approach, it is assumed that the implementation issues instructions out of an instruction window.…”

Section: Miscellaneousmentioning

confidence: 99%

Precise interrupts

Moudgill

Vassiiadis²

1996

IEEE Micro

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Interrupts and in particular precise interrupts constitute an integral part of all computer architectures. Implementing precise interrupts can substantially inhibit the performance of computers. To gain some insight into the problem, we divide common interrupts into four classes, and examine the cost of implementing precise interrupts. Two of these classes, external-critical and external-error, can be implemented cheaply on a pipelined processor, with little or no impact on performance. We propose that interrupts be implemented imprecisely, except during debugging, of a third class of interrupts, internal-error interrupts. Finally, we introduced some techniques that can be used to cheaply implement precise interrupts for the fourth class of interrupts, internal-critical interrupts, but may not apply generally. While the central concern is precision, or lack thereof, we also deal with several peripheral issues that arise when implementing interrupts on aggressive implementations. These include sparse restart, which will arise whenever we weaken the requirements for precision on an out-of-order issue processor, and the impact of parallel (e.g., superscalar) issue.

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“…The restart mechanism illustrated in Fig. 5 is that suggested by [10]. In this approach, it is assumed that the implementation issues instructions out of an instruction window.…”

Section: Miscellaneousmentioning

confidence: 99%

Precise interrupts

Moudgill

Vassiiadis²

1996

IEEE Micro

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“…It has been known for quite some time that hardwaremanaged TLBs outperform software-managed TLBs [10], [25]. Nonetheless, most modern high-performance architectures use software-managed TLBs (e.g., MIPS, Alpha, SPARC, PA-RISC), not hardware-managed TLBs (e.g.…”

Section: The Persistence Of Software-managed Tlbsmentioning

confidence: 99%

“…Torng and Day discuss an imprecise-interrupt mechanism appropriate for handling interrupts that are transparent to application program semantics [25]. The system considers the contents of the instruction window (i.e., the reorder buffer) part of the machine state and, so, this information is saved when handling an interrupt.…”

Section: Related Workmentioning

confidence: 99%

In-line interrupt handling and lock-up free translation lookaside buffers (TLBs)

Jaleel

Jacob

2006

IEEE Trans. Comput.

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“…These include the "length counter" technique of the IBM System/370 [28], the "invisible exchange package" of the CDC STAR-100 [36], the "instruction window" approach of Torng and Day [39], and the "replay buffer" approach of Rudd [33]. While these mechanisms provide full exception support, they expose microarchitectural details and are likely too complex for GPUs.…”

Section: Related Workmentioning

confidence: 99%

iGPU: Exception support and speculative execution on GPUs

Menon

Kruijf

Sankaralingam

2012

2012 39th Annual International Symposium on Computer Architecture (ISCA)

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Since the introduction of fully programmable vertex shader hardware, GPU computing has made tremendous advances. Exception support and speculative execution are the next steps to expand the scope and improve the usability of GPUs. However, traditional mechanisms to support exceptions and speculative execution are highly intrusive to GPU hardware design. This paper builds on two related insights to provide a unified lightweight mechanism for supporting exceptions and speculation on GPUs.First, we observe that GPU programs can be broken into code regions that contain little or no live register state at their entry point. We then also recognize that it is simple to generate these regions in such a way that they are idempotent, allowing their entry points to function as program recovery points and enabling support for exception handling, fast context switches, and speculation, all with very low overhead. We call the architecture of GPUs executing these idempotent regions the iGPU architecture. The hardware extensions required are minimal and the construction of idempotent code regions is fully transparent under the typical dynamic compilation framework of GPUs. We demonstrate how iGPU exception support enables virtual memory paging with very low overhead (1% to 4%), and how speculation support enables circuit-speculation techniques that can provide over 25% reduction in energy.

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Interrupt handling for out-of-order execution processors

Cited by 17 publications

References 9 publications

Precise interrupts

Precise interrupts

In-line interrupt handling and lock-up free translation lookaside buffers (TLBs)

iGPU: Exception support and speculative execution on GPUs

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