Interrupt Enabled Priority Based Master Slave Communication using SPI Protocol

Abstract

Serial Peripheral Interface or SPI is a synchronous serial communication protocol that provides full – duplex communication at very high speeds. It is a master – slave type protocol that provides a simple and low-cost interface between a microcontroller and its peripherals. This paper proposes the design of a priority-based master slave communication system using SPI Protocol that enables the system to operate using interrupts. The design mainly emphasizes on priority-based communication where the slaves will generate an interrupt over a newly defined interrupt pin when some data transfer needs to happen. When the master receives an interrupt from the slave it establishes communication with one slave at a time based on the priority and the priority to each slave is assigned by the arbiter or priority control block. The highest priority slave is served first. Shift register is used to store and transfer the data bit by bit and it resets every time a data transfer is complete. The design proposed here can be implemented in different applications which involve the peripherals that can support SPI protocol for communication such as LCDs, Analog to Digital Converter, Digital to Analog Converter, Memory Cards, Temperature Sensor, Pressure Sensor. In this work, a single master multi slave architecture is considered. The design given in this paper can be scaled up to support more than four slaves.

Design and verification of daisy chain serial peripheral interface using system Verilog and universal verification methodology

“…However, the number of chip-select lines are increased in the SPI conventional method, while in the daisy chain technique, the number of chip-select lines is reduced in implementation and easy to design [5]- [21]. The master-slave communication protocol is designed by assigning the priority to each slave by communicating with the master based on the highest priority slave [6]- [23]. However, the design will consume less power and utilization sources compared with the other complex design.…”