Interrelation of the CdTe Grain Size, Postgrowth Processing, and Window Layer Selection on Solar Cell Performance

Abstract

Recent improvements to the CdTe solar cell device structure have focused on replacing the CdS window layer with a more transparent material to reduce parasitic absorption and increase J sc, as well as incorporating selenium into the absorber layer to achieve a graded band gap. However, altering the CdTe device structure is nontrivial due to the interdependent nature of device processing steps. The choice of the window layer influences the grain structure of the CdTe layer, which in turn can affect the chloride treatment, which itself may contribute to intermixing between the window and absorber layers. This work studies three different device architectures in parallel, allowing for an in-depth comparison of processing conditions for CdTe solar cells grown on CdS, SnO2, and CdSe. Direct replacement of the CdS window layer with a wider band gap SnO2 layer is hindered by poor growth of the absorber, producing highly strained CdTe films and a weak junction. This is alleviated by inserting a CdSe layer between the SnO2 and CdTe, which improves the growth of CdTe and results in a graded CdSe x Te1–x absorber layer. For each substrate, the CdTe deposition rate and postgrowth chloride treatment are systematically varied, highlighting the distinct processing requirements of each device structure.

Toward Development of CdZnTe and CdMnTe Thin Film‐Based Solar Cells: Optimized Properties and a Comparative Performance Exploration

“…QE measurement can be used to probe the mechanism underlying the performance changes brought on by grain size and post‐growth treatment. [ 41 ] The voltage dependence of the collection efficiency, series resistance, the electrical barrier of the back contact, photo‐conductive effects in the window and absorber layers, and any secondary barriers in the primary junction can all have an impact on the quantum efficiency measurement of CZT and CMT PV cells (when measuring under forwarding voltage). Although each of these indicators has a unique signature, misinterpretation is conceivable and possibly prevalent without precise measurements of these elements.…”

Reactive DC Sputtered TiO2 Electron Transport Layers for Cadmium‐Free Sb2Se3 Solar Cells

“…During the transition to metal oxide ETLs, CdTe devices similarly struggled with charge accumulation at the ETL/absorber interface and resulting J-V distortion, [11,[57][58][59][60][61][62] which was eventually alleviated through interface engineering with CdSe x Te 1-x (CST) absorber grading at the junction. The current record TiO 2 /Sb 2 (S,Se) 3 device similarly benefited from absorber grading with a sulfur-rich junction to suppress interfacial carrier recombination.…”