The grain structure of 1.2 µm electroplated Cu layers with undoped Cu seed layer has been investigated using electron backscatter diffraction (EBSD). Therefore orientation imaging microscopy (OIM) was carried out on samples with five different liner systems (Ti, Ta, WTi, TiN and TaN), three different annealing steps (self-anneal at room temperature, 1 h at 110 °C and 0.5 h at 380 °C) and two plating chemistries with varying acid content. In addition, samples with 1 µm and 3 µm electroplated Cu on an Al-doped Cu seed layer have been analyzed in order to investigate the influence of the plated layer thickness on grain structure.The results show that the grain structure is dominated by low energy CSL boundaries, especially Σ3 twins, which can be found in almost every grain. This twinning causes a typical deviation from the expected {111} orientation parallel to the sample surface towards {115} orientations. This is the result of the self-annealing process (caused by recrystallization).Differences in orientation caused by the liner system will be shown as well as influences of the Cu-plating thickness on the fraction of {101} orientations. Finally, changes in grain size and twinning fraction due to subsequent annealing steps will be presented.
IntroductionSince Cu was successfully implemented in semiconductor processes, the variety of applications of Cu based devices has grown steadily. With its higher electrical and thermal conductivity, its better thermal stability and its smaller coefficient of thermal expansion compared to Al, Cu pushed the limits for clock frequencies and power consumption for semiconductor devices. In frontend applications the Cu grain size gains more and more importance on the overall performance and reliability of the interconnect system [1-2]. Apart from the importance for frontend applications, the development of highly integrated 3D systems, as well as power applications creates a need for Cu based backend technologies, such as direct Cu-Cu Bonding and Cu to Cu wire bonding. The properties of Cu such as surface oxidation or the mechanical behavior like hillock formation and Cu protrusion in through silicon vias (TSV) are only some of the challenges, which need further process related investigations on microstructure in order to make Cu based interconnection technologies more reliable.Cu thin films are deposited by electrochemical deposition because of its good filling properties (compared to physical vapor deposition), its availability due to the frontend applications, and the fast and cost efficient process implementation. The resulting grain structure undergoes a so called self-annealing process after plating that causes a microstructure evolution at room temperature accompanied by decreasing resistance and hardness [3][4][5][6][7][8]. Investigations by