Interpolation in digital modems. I. Fundamentals

Gardner, F. F.

doi:10.1109/26.221081

Cited by 520 publications

(161 citation statements)

References 5 publications

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“…El procesador de sincronización puede ser llevado a cabo por medio de un NCO [7]. El registro del NCO se calcula iterativamente por: Ecuación 8 Y el retardo fraccional se estima mediante: Ecuación 9 El prototipo trabaja con dos muestras/símbo-lo en el transmisor y en el receptor, de modo que nominalmente T I/ T S =1.…”

Section: Control Del Interpolador Y Ncounclassified

mplementación en FPGA de un sistema totalmente digital de recuperación de reloj

Cardenas

Arévalo

2011

ings

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ResumenLa recuperación de la señal de reloj y de datos CDR es un subsistema importante de cada dispositivo de comunicaciones dado que el receptor debe recuperar la información exacta del reloj del transmisor, misma que está usualmente codificada dentro de la trama de datos entrante. Se han desarrollado algunas técnicas analógicas para CDR basadas en la teoría de PLLs empleando un VCO externo. Sin embargo, en algunas ocasiones la conexión del núcleo digital (FPGA, DSP) con los componentes externos puede resultar complicada. De este modo, el núcleo digital es también utilizado para solventar la tarea de la recuperación de la señal de reloj mediante técnicas totalmente digitales, sin el uso de un VCO externo. El presente artículo describe un subsistema totalmente digital de recuperación de señal de reloj, implementado en un FPGA.

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Section: Control Del Interpolador Y Ncounclassified

mplementación en FPGA de un sistema totalmente digital de recuperación de reloj

Cardenas

Arévalo

2011

ings

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“…The received waveform is initially sampled at intervals of T s and stored into a buffer. The interpolator computes interpolants at intervals of T i using linear interpolation, which are then used for the matched filtering process [14]. In this work, we use T i =T /2 and T s =T /4, whereT is the receiver-side assumption of the transmitter symbol periodT (i.e.…”

Section: Symbol Timing Recoverymentioning

confidence: 99%

Carrier and Timing Synchronization of BPSK via LDPC Code Feedback

Valles

Wesel

Villasenor

et al. 2006

2006 Fortieth Asilomar Conference on Signals, Systems and Computers

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Abstract-In traditional receiver architectures, symbol acquisition and tracking are performed using phase lock techniques that are independent of the channel-code decoding process. In [1] feedback from the constraint-node side of a bi-partite graph is used to estimate symbol frequency and timing offset in a baseband pilotless transmission. In [2] soft information feedback from an LDPC decoder is used to recover carrier phase information under the assumption of perfect symbol timing. In this paper we address the problem of joint carrier-phase and symbol timing recovery. The proposed system is able to perform within 0.3 [dB] of the code performance with perfect knowledge of carrier phase and symbol timing.

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“…The received waveform is initially sampled at intervals of T s and stored into a buffer. The interpolator computes interpolants at intervals of T i using linear interpolation, which are then used for the matched filtering process [5]. In this work, we use T i =T /2 and T s =T /4, whereT is the receiver-side assumption of the transmitter symbol period T (i.e.…”

Section: Timing Error Modalitiesmentioning

confidence: 99%

Joint LDPC decoding and timing recovery using code constraint feedback

Lee¹,

Valles²,

Villasenor³

et al. 2006

IEEE Commun. Lett.

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Abstract-Timing recovery and channel decoding are traditionally performed independently. However, we show here that the information generated during the iterative decoding of LowDensity Parity-Check (LDPC) coded data can be fed back to the timing recovery circuit to enable accurate estimation of frequency and phase errors without the need for any pilot symbols. We describe a method capable of handling large offsets with complexity that grows linearly with offset size. Combining the LDPC constraint node observations with a properly calibrated phase locked loop allows successful tracking of a constant time delay, a frequency offset and a random phase walk.

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Interpolation in digital modems. I. Fundamentals

Cited by 520 publications

References 5 publications

mplementación en FPGA de un sistema totalmente digital de recuperación de reloj

mplementación en FPGA de un sistema totalmente digital de recuperación de reloj

Carrier and Timing Synchronization of BPSK via LDPC Code Feedback

Joint LDPC decoding and timing recovery using code constraint feedback

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