Interplay Between Statistical Variability and Reliability in Contemporary pMOSFETs: Measurements Versus Simulations

Abstract

This paper presents an extensive study of the interplay between as-fabricated (time-zero) variability and gate oxide reliability (time-dependent variability) in contemporary pMOSFETs. We compare physical simulation results using the atomistic simulator GARAND with experimental measurements. The TCAD simulations are accurately calibrated to reproduce the average transistor behavior. When random discrete dopants, line edge roughness, and gate polysilicon granularity are considered, the simulations accurately reproduce time-zero (as-fabricated) statistical variability, as well as time-dependent variability data, represented by threshold voltage shift distributions. The calibrated simulations are then used to predict the reliability behavior at different bias conditions and for different device dimensions.Index Terms-Atomistic doping, random telegraph noise (RTN), reliability, statistical simulations.

Correlated Time-0 and Hot-Carrier Stress Induced FinFET Parameter Variabilities: Modeling Approach

“…Investigations conducted by Kerber et al [ 7 , 8 ] resulted in a correlation between distributions of the threshold voltage in unstressed devices and threshold voltage changes induced by bias temperature instability (BTI). Quite to the contrary, Angot et al [ 9 ] and Hussin et al [ 10 ] did not reveal any correlation between time-0 values and their BTI-induced shifts . The latter group has been very actively studying the correlation between time-0 and stress induced variabilities also in the context of self-heating [ 11 ] and random dopant induced percolation paths in FETs [ 12 ].…”