Internal Chip ESD Phenomena Beyond the Protection Circuit

Latchup in voltage tolerant circuits: a new phenomenon

“…In addition, the recent trend for high volume CMOS technologies has been to use non-EPI substrates for cost-effective processes. While these high resistance substrates are helpful for efficient ESD design they introduce reliability issues, such as parasitic device interactions during ESD [6,7], EOS due to an easier over-voltage trigger, and unexpected latchup issues. The so-called standard latchup specified by JEDEC standards is well understood and is well controlled with guard-ring protection design; how- ever, some other parasitic effects are now beginning to be observed [8].…”

Design of local ESD clamp for cross-power-domain interface circuits

“…To evaluate the ESD robustness of the chip, the ESD tests across separated power domains are also specified in the ESD-test standards [1]. These ESD tests may cause damages at cross-power-domain interface circuits beyond the ESD protection circuits of I/O cells [2,3]. Therefore, several ESD protection designs have been presented to avoid ESD damages at the cross-powerdomain interface circuits [4,5,6,7].…”

Effect of Electrostatic Discharge on Digital and Analog Circuits

“…Many components in the circuits are very robust, can handle the discharge and undergo upsets. But if a part has a small or thin geometry as part of their physical structure then the voltage can break down that part of the semiconductor [5][6][7][8]. Currents during the ESD events become quite high, but are in the nanosecond to microsecond time frame.…”