Intermediately executed code is the key to find refactorings that improve temporal data locality

Beyls, Kristof; D’Hollander, Erik H.

doi:10.1145/1128022.1128071

Cited by 17 publications

(18 citation statements)

References 37 publications

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“…However, the authors of these papers do not discuss the details of how they obtained the results on profiling. Also, Beyls et al visualize loop nest structures in the form of nested loop forests [30], but the scope of loop nests is limited to a single procedure call because it is based on static analysis.…”

Section: Related Workmentioning

confidence: 99%

Identifying Program Loop Nesting Structures during Execution of Machine Code

Sato

Inoguchi

Nakamura

2014

IEICE Trans. Inf. & Syst.

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SUMMARYThis paper presents a mechanism for detecting dynamic loop and procedure nesting during the actual program execution on-the-fly. This mechanism aims primarily at making better strategies for performance tuning or parallelization. Using a pre-compiled application executable machine code as an input, our mechanism statically generates simple but precise markers that indicate loop entries and loop exits, and dynamically monitors loop nesting that appears during the actual execution together with call context tree. To keep precise loop structures all the time, we monitor the indirect jumps that enter the loop regions and the setjmp/longjmp functions that cause irregular function call transfers. We also present a novel representation called Loop-Call Context Graph that can keep track of inter-procedural loop nests. We implement our mechanism and evaluate it using SPEC CPU2006 benchmark suite. The results confirm that our mechanism can successfully reveal the precise inter-procedural loop nest structures from all of SPEC CPU2006 benchmark executions without any particular compiler support. The results also show that it can reduce runtime loop detection overheads compared with the existing loop profiling method. key words: dynamic loop nests, loop-call context tree, on-the-fly loop detection

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Section: Related Workmentioning

confidence: 99%

Identifying Program Loop Nesting Structures during Execution of Machine Code

Sato

Inoguchi

Nakamura

2014

IEICE Trans. Inf. & Syst.

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“…Beyls and D'Hollander [5] describe RDVIS, a tool for visualizing reuse distance information clustered based on the intermediary executed code (IEC) between two accesses to the same data, and SLO, a tool that suggests locality optimizations based on the analysis of the IEC. The capabilities of their tools are similar to those we describe in this paper.…”

Section: Related Workmentioning

confidence: 99%

Pinpointing and Exploiting Opportunities for Enhancing Data Reuse

Marin

Mellor-Crummey

2008

ISPASS 2008 - IEEE International Symposium on Performance Analysis of Systems and Software

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Abstract-The potential for improving the performance of data-intensive scientific programs by enhancing data reuse in cache is substantial because CPUs are significantly faster than memory. Traditional performance tools typically collect or simulate cache miss counts or rates and attribute them at the function level. While such information identifies program scopes that exhibit a large cache miss rate, it is often insufficient to diagnose the causes for poor data locality and to identify what program transformations would improve memory hierarchy utilization. This paper describes an approach that uses memory reuse distance to identify an application's most significant memory access patterns causing cache misses and provide insight into ways of improving data reuse. Unlike previous approaches, our tool combines (1) analysis and instrumentation of fully optimized binaries, (2) online analysis of reuse patterns, (3) fine-grain attribution of measurements and models to statements, loops and variables, and (4) static analysis of access patterns to quantify spatial reuse. We demonstrate the effectiveness of our approach for understanding reuse patterns in two scientific codes: one for simulating neutron transport and a second for simulating turbulent transport in burning plasmas. Our tools pinpointed opportunities for enhancing data reuse. Using this feedback as a guide, we transformed the codes, reducing their misses at various levels of the memory hierarchy by integer factors and reducing their execution time by as much as 60% and 33%, respectively.

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“…Beyls and D'Hollander [9] describe RDVIS, a tool for visualizing reuse distance information clustered based on the intermediary executed code (IEC) between two accesses to the same data, and SLO, a tool that suggests locality optimizations based on the analysis of the IEC. The capabilities of their tools are similar to those we describe in this paper.…”

Section: Techniques For Understanding Performance Bottlenecksmentioning

confidence: 99%

Application Insight Through Performance Modeling

Marin

Mellor-Crummey

2007

2007 IEEE International Performance, Computing, and Communications Conference

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Tuning the performance of applications requires understanding the interactions between code and target architecture. Hardware counters, present in all modern processors, can identify possible causes of performance problems and can pinpoint sections of code that execute at a low fraction of machine peak performance. However, the information provided by hardware counters is often insufficient to understand the causes of poor performance or to realistically estimate the potential for performance improvement.This thesis presents techniques to measure and model application characteristics independent of the target architecture. Using information gathered from both static and dynamic analysis, this approach not only makes accurate predictions about the behavior of an application on a target architecture for different inputs, but also provides guidance for tuning by highlighting the factors that limit performance at different points in a program. We introduce several new performance analysis metrics that estimate the maximum gain expected from tuning different aspects of an application, or from using hardware accelerator coprocessors. Our approach models the most important factors affecting application performance and provides estimates of unfulfilled performance potential due to a mismatch between an application's characteristics and the resources present on the target architecture. We model an application's instruction execution cost and memory hierarchy utilization, and we identify performance problems arising from insufficient instruction-level parallelism or poor data locality.To demonstrate the utility of this approach, this thesis presents the results of analyzing and tuning two scientific applications. For Sweep3D, a three-dimensional Cartesian geometry neutron transport code benchmark from the DOEs Accelerated Strategic Computing Initiative, our analysis identified opportunities for improvement that shortened execution time by 66% on an Itanium2-based system. For the Gyrokinetic Toroidal Code (GTC) from Princeton Plasma Physics Laboratory, a particlein-cell code that simulates turbulent transport of particles and energy in burning plasma, our techniques identified opportunities for improvement that shortened execution time by 33% on the same Itanium2 system.

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Intermediately executed code is the key to find refactorings that improve temporal data locality

Cited by 17 publications

References 37 publications

Identifying Program Loop Nesting Structures during Execution of Machine Code

Identifying Program Loop Nesting Structures during Execution of Machine Code

Pinpointing and Exploiting Opportunities for Enhancing Data Reuse

Application Insight Through Performance Modeling

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