Intermediate Level FPGA Reconfiguration for an Online EHW Pattern Recognition System

Abstract

We propose a field programmable gate array (FPGA) implementation for a run-time adaptable evolvable hardware classifier system. Previous implementations have been based on a high-level virtual reconfigurable circuit technique which requires many FPGA resources. We therefore apply an intermediate level reconfiguration technique which consists of using the FPGA lookup tables as shift registers for reconfiguration purposes. This leads to significant resource savings, reducing the classifier circuit size to less than one third of the original implementation. This in turn has made it possible to implement a larger, more accurate classifier than before, giving 97.5% recognition accuracy for a face image application. Experiments also show that a reduction of data element resolution can lead to further resource savings while still maintaining high classification accuracy.

Investigating evolvable hardware classification for the BioSleeve electromyographic interface

“…III, the B 11 instance of the classifier requires a moderate amount of FPGA resources. Moreover, results from [23] suggest that even smaller implementations should be possible using special techniques, without sacrificing classification accuracy. As an instance of the B 17 dataset would benefit from more resources, both in terms of a higher number of categories and a higher number of FU rows for improved accuracy, it would be beneficial to further investigate some methods for reducing the resource footprint.…”

“…Here, the training module was implemented on an on-chip CPU, but the simplified evolutionary process considered in this paper would open up for a full hardware implementation, similar to the one reported in [22]. Implementation details of the reconfigurable functional units can be found in [23]. The implementation of the feature extraction module has not been considered in this paper.…”

“…The implementation follows the VRC-based approach described in [23]. We chose to implement an instance of the B 11 classifier, with 16 rows per classifier as a tradeoff between accuracy and resource requirements.…”

A fast Reconfigurable 2D HW core architecture on FPGAs for evolvable Self-Adaptive Systems

“…This is due to the large gra reconfigurable regions (to change the nu the CDM, the full module has to be limited use of the ICAP control, improvements. A different approach is same group in [13] that exploits the SRL b Virtex devices LUTs to change its logic, w use the normal configuration interfaces, li this case, the reconfiguration process is ca shifting the configuration bits into t alternative achieves a higher reconfi enough to fulfill the application requireme overhead compared with VRCs. Howeve very device dependent, and reconfigurabi adapt LUT functions.…”

“…Modularity also allo and synthesis of each PE independ modular design flow [16]. The commercial flow reduces the depen details of the device, mainly com reconfiguration approaches [13]-[ previous section. In addition to programs, an ad-hoc tool has also the partial bitstream that correspo modules of the architecture are defi area with the same dimensions.…”