Interlock schemes for micropipelines: application to a self-timed rebound sorter

Karthik, S.; Souza, Isaac D. T. de; Rahmeh, J.T.; Abraham, J.A.

doi:10.1109/iccd.1991.139927

Cited by 2 publications

(2 citation statements)

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“…Although the control structure for a micropipeline can be enhanced by using additional elements, this is a fairly complex and error-prone activity. While several micropipelined solutions to specific circuit structures have been developed [17,18,19], including a complete asynchronous microprocessor [20], a general, higher-level method for designing micropipeline control circuits is essential.…”

Section: Micropipelinesmentioning

confidence: 99%

Asynchronous design methodologies: an overview

1995

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Asynchronous design has been an active area of research since at least the mid 1950's, but has yet to achieve widespread use. We examine the benefits and problems inherent in asynchronous computations, and in some of the more notable design methodologies. These include Huffman asynchronous circuits, burst-mode circuits, micropipelines, template-based and trace theory-based delay-insensitive circuits, signal transition graphs, change diagrams, and compilation-based quasidelay-insensitive circuits.

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Section: Micropipelinesmentioning

confidence: 99%

Asynchronous design methodologies: an overview

1995

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“…Even though theoretical log-depth and somewhat more practical log 2 -depth sorting networks are widely known [13], most hardware implementations of sorting are based on a linear array structure in view of its simplicity and ease of VLSI realization [16]. Pipelined schemes, such as rebound sorting [2], [4], [5], up/down sorting [8], enumeration sorting (via counting) [15], and balanced heap sorting [9], have been proposed on linear arrays. To implement a stable sorting algorithm, however, it is often assumed that an entry number or input order index is included with each record.…”

Section: Introductionmentioning

confidence: 99%

Data-driven control scheme for linear arrays: application to a stable insertion sorter

Parhami

Kwai²

1999

IEEE Trans. Parallel Distrib. Syst.

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Abstract-We present a strategy for designing stable insertion sorters based on linear arrays with data-driven control. The novelty of our approach lies in each data item carrying a control tag to specify how it is to be operated upon by a receiving cell and in performing two parallel comparisons within each cell. To assure first-in/first-out handling of equal key values, some data items must be marked to reflect their past histories. Such marking is conveniently carried out by modifying the data item's control tag. It is the combination of the above features that allows us to derive the first single-cycle priority queue that operates in fully pipelined mode, with no broadcasting of data values or control signals. By performing more than two parallel comparisons in each cell, the VLSI implementation cost of our stable sorter can be reduced. We show that highly cost-effective designs can be obtained by selecting an optimal cell size in terms of the number of comparators it contains.

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Interlock schemes for micropipelines: application to a self-timed rebound sorter

Cited by 2 publications

References 5 publications

Asynchronous design methodologies: an overview

Asynchronous design methodologies: an overview

Data-driven control scheme for linear arrays: application to a stable insertion sorter

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