Interfacial properties of single-crystalline CeO2 high-k gate dielectrics directly grown on Si (111)

Abstract

Interfacial properties of single-crystalline CeO2 high-k dielectrics directly grown on Si (111) were investigated by comparing metal–insulator–semiconductor field-effect transistors (MISFETs) without any interfacial layer [(w/o-IL); direct growth of CeO2 on Si] and those with an interfacial layer (w-IL). FET characteristics, such as the drain current and the S factor, for the w/o-IL MISFET were much worse than those for the w-IL MISFET. The in-gap states attributed to the oxygen defects were detected in the CeO2 directly grown on Si by x-ray photoelectron spectroscopy measurements. The large interface state density induced by the oxygen defects at the CeO2/Si interface may deteriorate the w/o-IL MISFET performances.

Silicate-free growth of high-quality ultrathin cerium oxide films on Si(111)

“…These low-k defect phases give rise to significant interfacial charge trapping while lowering the dielectric constant of the film and increasing the effective oxide thickness (EOT) of the metal insulator semiconductor field-effect transistor (MISFET) structure. 6 Consequently, previous attempts in direct growth of CeO 2 on Si(111) have resulted in worse MISFET performance with respect to saturation drain current and subthreshold behavior, effectively making intentionally postoxidized stack structures with a considerably thickened amorphous interface layer still more attractive. 6 Hence, fabrication of a defect-free, high-k, epitaxial interface layer remains of crucial importance for the realization of novel MISFET structures with further decreased EOTs.…”

“…Conceivable routes to overcome the challenges presented by the high reactivity at the oxide-silicon interface could, in principle, range from attempts to influence the growth kinetics by varying the ceria growth rate, oxygen partial pressure, and substrate temperature 14 to approaches that incorporate surface active agents, e.g., hydrogen, 6,14,15 to stabilize the interface before reactive cerium deposition in an oxygen background. The latter option, unfortunately, carries the disadvantage that the relatively low desorption temperature of hydrogen from silicon [about 450…”

Advanced CMOS Gate Stack: Present Research Progress

“…Now it has been recognized that the family of hafnium oxide-based materials (e.g., HfO 2 , HfSi x O y , and HfSi x O y N z ) emerges as a leading candidate to replace SiO 2 gate dielectrics in advanced CMOS applications [7,8]. There are a number of high-k dielectrics that have been and/or are actively being pursued for replacing SiO 2 3 , and rare-earth scandates LaScO 3 , GdScO 3 , DyScO 3 , and SmScO 3 [9][10][11][12][13].…”

Ultrathin, epitaxial cerium dioxide on silicon

“…In addition to their use in research thrust areas like heterogeneous catalysis, renewable energy conversion, and storage, 1 some of the REO have attracted a lot of interest in the field of microelectronics due to their high static dielectric constants k and comparatively large band gaps, making them promising alternative materials for "high-k" gate dielectrics replacing the traditional SiO 2 . [2][3][4] To this end, a particularly interesting candidate is CeO 2 , whose dielectric constant 5,6 exceeds a value of k > 26 and which exhibits a band gap 7,8 of $6 eV. Furthermore, the almost perfect lattice match between silicon and CeO 2 ðDa 0 =a 0 ¼ 0:36%Þ suggests the possibility of realizing an epitaxial, well-ordered, and sharp ceria-silicon interface.…”

“…6,20,21 In this respect, passivation seems very promising since it may effectively facilitate the suppression of in-gap states associated with oxygen defects at the ceria-silicon interface. 5 However, hydrogen limits the growth temperature to 450 C due to its relatively low desorption temperature, 22 motivating the search for other adsorbates that would allow for higher growth temperatures because at given interface stability higher growth temperatures directly translate into an increased crystallinity of the deposited REO film. Recently, we have shown that the use of chlorine, which is commonly used in semiconductor processing, 23 for substrate passivation enables the growth of well-ordered Ce 2 O 3 (111) adlayers on Si(111) by reactive molecular beam epitaxy (MBE) in ultra-high vacuum (UHV), with Cl predominantly remaining at the oxide-silicon interface.…”