Interface trap and oxide charge generation under negative bias temperature instability of p-channel metal-oxide-semiconductor field-effect transistors with ultrathin plasma-nitrided SiON gate dielectrics

Abstract

The interface trap generation ͑⌬N it ͒ and fixed oxide charge buildup ͑⌬N ot ͒ under negative bias temperature instability ͑NBTI͒ of p-channel metal-oxide-semiconductor field-effect transistors ͑pMOSFETs͒ with ultrathin ͑2 nm͒ plasma-nitrided SiON gate dielectrics were studied using a modified direct-current-current-voltage method and a conventional subthreshold characteristic measurement. Different stress time dependences were shown for ⌬N it and ⌬N ot. At the earlier stress times, ⌬N it dominates the threshold voltage shift ͑⌬V th ͒ and ⌬N ot is negligible. With increasing stress time, the rate of increase of ⌬N it decreases continuously, showing a saturating trend for longer stress times, while ⌬N ot still has a power-law dependence on stress time so that the relative contribution of ⌬N ot increases. The thermal activation energy of ⌬N it and the NBTI lifetime of pMOSFETs, compared at a given stress voltage, are independent of the peak nitrogen concentration of the SiON film. This indicates that plasma nitridation is a more reliable method for incorporating nitrogen in the gate oxide.

Influence of bulk bias on negative bias temperature instability of p-channel metal-oxide-semiconductor field-effect transistors with ultrathin SiON gate dielectrics

“…The E a value of the normal NBT stress is in consistent with that reported in literature. 9,14,20 On the other hand, the hot hole injection induced degradation has a very small E a value, both for the V b positive bias in the static stress and the V b floating in the bipolar stress, in agreement with our model.…”

“…⌬V th has an approximately similar trend to that of ⌬N it but with a slight different slope, indicating the fact that the created oxide charge is not one-to-one related with the interface trap. 20 At the V a = 2.8 V stress, the saturation effect appears at the very earlier stress times due to the large ⌬N it . The degradation saturation effect can be explained by the limited Si-H bond number in the SiO 2 / Si interface.…”

“…1 for a pMOSFET before and after NBT stress from 3 to 5000 s. By increasing the stress time, the DCIV peak height increases and the peak position shifts to the negative direction, reflecting the interface trap generation and the fixed oxide charge buildup, respectively. 20…”

Mechanism of Dynamic Bias Temperature Instability in p- and nMOSFETs: The Effect of Pulse Waveform

“…The initial N it of fresh devices is around 1.5−3.0 × 10 9 cm −2 for pMOSFETs and around 4.4−8.0 × 10 9 cm −2 for nMOSFETs, as calculated from the DCIV peak height by assuming the carrier capture rate coefficient of 10 −8 cm 3 /s for all devices [22]. It should be noted that the uncertainty of this coefficient may result in a systematic error for the calculated N it value compared with that determined from other methods, but the relative value is true.…”

“…Devices were stressed at a temperature ranging from 30 to 150 • C by applying a dc or ac voltage on the gate electrode while the other electrodes (source, drain, and bulk) were grounded. The stress was interrupted at a predetermined period to measure the interface trap density (N it ) using a modified direct-current current-voltage (DCIV) method at the stress temperature [22], [23]. The temperature stability during whole stressing and sensing process is better than ±1 • C. Each stress was carried out on a fresh device.…”