Interface Engineering for InGaAs n-MOSFET Application Using Plasma PH[sub 3]–N[sub 2] Passivation

Abstract

To realize high electron mobility metal-oxide-semiconductor field effect transistors ͑MOSFETs͒ on In 0.53 Ga 0.47 As with unpinned Fermi level, a PH 3 -N 2 plasma treatment is proposed and preliminarily studied as a novel interface engineering technique, which passivates the InGaAs surface by depositing a phosphorus nitride ͑P x N y ͒ layer to suppress AsO x and free As. Comparative X-ray photoelectron spectroscopy and atomic force microscopy studies reveal that a low pressure PH 3 -N 2 plasma treatment of In 0.53 Ga 0.47 As results in a smooth and atomically thin ͑ϳ1 monolayer͒ P x N y film as a main product, with a P-for-As anion exchanged layer found beneath the P x N y layer in a practically wide range of process window. The process conditions affect the stoichiometry of the P x N y layer, the amount of phosphorus and nitrogen atoms incorporated, and the degree of the P-for-As exchange reaction. MOSFET devices integrated with metalorganic chemical vapor deposited HfO 2 /TaN metal gate on the passivated In 0.53 Ga 0.47 As substrates have been fabricated by the conventional self-aligned gate-first process and compared to nonpassivated MOSFETs. The excellent interface quality of P x N y passivated In 0.53 Ga 0.47 As/HfO 2 /TaN gate stack has been proven showing suppressed frequency dispersion in inversion capacitance by 82-94% compared to the nonpassivated device and a low subthreshold slope approaching the theoretical value of 60 mV/dec.

Surface passivation and aging of InGaAs/InP heterojunction phototransistors

“…It is considered that the main deleterious influence to induce the band bending is due to the volatile V oxide species. 27 The normalized As3d XPS spectrum of the In 0.53 Ga 0.47 As surface is exemplified in the control sample as shown in Fig. 5(a).…”

Gate-Leakage and Carrier-Transport Mechanisms for Plasma-PH3 Passivated InGaAs N-Channel Metal–Oxide–Semiconductor Field-Effect Transistors

“…The thicker interfacial layer of passivated device compared to non-passivated device is believed to be contributed mostly by the passivation layer which consists of phosphorus nitride (P x N y ) and P-for-As layer. 5) Hence, despite having a larger EOT of 1.9 nm for non-passivated compared to 1.7 nm for passivated device, the presence of interdiffusion of Ga/As/ O elements at the HfAlO/In 0:53 Ga 0:47 As interface explains the observed larger gate leakage current level for nonpassivated compared to passivated device in the substrate injection region. The inset of Fig.…”

“…[1][2][3][4] From our previous works, we have shown the improvements made in the device characteristics as well as mechanism of plasma-PH 3 passivation treatment. 5) However, understanding of how this treatment is effective in improving the device performance in terms of studying the various mechanisms such as gate leakage and carrier-transport mechanism have yet to be investigated systematically. The importance of this is that a detailed knowledge of gate leakage and carrier transport can give insight to defects that are present in the oxide or at the high-k/In 0:54 Ga 0:47 As interface, and thus allows further improvements to be made to the gate stack.…”

Multiple-Gate In0.53Ga0.47As Channel n-MOSFETs with Self-Aligned Ni-InGaAs Contacts

“…Indium Gallium Arsenide (In-GaAs) is an attractive channel material for metal-oxide-semiconductor field-effect transistors (MOSFETs) due to its much higher electron mobility than Si. [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19] Promising results on InGaAs channel FinFETs have been achieved recently. [20][21][22][23][24] However, high source/drain (S/D) series resistance (R SD ) may affect the drive current performance of FinFETs.…”