2008
DOI: 10.1063/1.2844483
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Interface engineering for high interfacial strength between SiCOH and porous SiCOH interconnect dielectrics and diffusion caps

Abstract: The integration of low- and ultralow-k SiCOH dielectrics in the interconnect structures of very large scale integrated chips involves complex stacks with multiple interfaces. Successful fabrication of reliable chips requires strong adhesion between the different layers of the stacks. A critical interface in the dielectric stack is the interface between the SiCNH diffusion cap and the SiCOH inter- and intralevel dielectrics (ILDs). It was observed that, due to the original deposition conditions, the interface l… Show more

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Cited by 44 publications
(27 citation statements)
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“…12,13 Nanoporous OSG capped with a SiCN diffusion barrier constitutes an important model system for future generations of microelectronic devices. 20 To the best of our knowledge, an integrated study of this material system focusing on water diffusion and its impact on fracture is yet to be conducted. In this study, we first characterize the effect of water exposure on the fracture behavior of the OSG and the OSG/SiCN interface.…”
Section: Introductionmentioning
confidence: 99%
“…12,13 Nanoporous OSG capped with a SiCN diffusion barrier constitutes an important model system for future generations of microelectronic devices. 20 To the best of our knowledge, an integrated study of this material system focusing on water diffusion and its impact on fracture is yet to be conducted. In this study, we first characterize the effect of water exposure on the fracture behavior of the OSG and the OSG/SiCN interface.…”
Section: Introductionmentioning
confidence: 99%
“…However, it was also acknowledged that the convergence of increasing porosity and decreasing device feature sizes would ultimately lead to severe integration issues for dielectric insulators with k < 2.7. [3][4][5][6] The resulting structural changes in both density and networkconnectivity (as compared to SiO 2 ) negatively impacted the mechanical properties of the porous low-k materials, [7][8][9][10][11][12][13] leading in some cases to drastic failure during chip packaging.…”
mentioning
confidence: 99%
“…Besides the location of the crack stop, the fracture resistance of the crack stop structure and low-k dielectrics is also important: more resistance means less susceptibility to fracture and larger process margin. In addition, several other techniques have been proposed to improve the mechanical reliability of low-k interconnect including optimization of the dicing process [24] and repair of dicing defects based on chemical reaction [25].…”
Section: B Implementation Of Crack Stop Structurementioning
confidence: 99%