Interface charge trapping and hot carrier reliability in high voltage SOI SJ LDMOSFET

Antoniou, Marina; Udrea, F.; Tee, Elizabeth Kho Ching; Yang, Hao; Pilkington, S. J.; Yaw, Kee Kia; Pal, D. K.; Hoelke, A.

doi:10.1109/ispsd.2011.5890859

Cited by 4 publications

(1 citation statement)

References 6 publications

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“…It can be seen that carriers near the drain are rather hot, thereby leading to a drain N it peak, cf. [16]. If one of the AB-or MVE-mechanisms is deactivated, this peak does not disappear, therefore we conclude that both processes are saturated.…”

Section: Bmentioning

confidence: 68%

Physical modeling of hot-carrier degradation in nLDMOS transistors

Wimmer¹,

Tyaginov

Rudolf

et al. 2014

2014 IEEE International Integrated Reliability Workshop Final Report (IIRW)

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Our physics-based HCD model has been validated using scaled CMOS transistors in our previous work. In this work we apply this model for the first time to a high-voltage nLDMOS device. For the calculation of the degrading behaviour the Boltzmann transport equation solver ViennaSHE is used which also requires high quality adaptive meshing. We discuss the influence of the different model components in the different device regions. Finally we compare the model to experimental degradation results and show that each one gives a significant contribution to the result and that all of them are needed in order to satisfactorily fit the experimental data. I. INTRODUCTIONThe LDMOS transistor is one of the most popular devices employed in mixed-signal integrated circuits and in highvoltage automotive applications [1]. Hot-carrier degradation (HCD) still remains one of the main reliability concerns in these devices [1], [2], [3], [4]. This makes a predictive physical model for HCD in LDMOS very attractive. At the same time, such a model is extremely challenging to develop because of the complexity of the HCD-phenomenon and the complicated topological structure of the LDMOS.In fact, the physical origin of HCD is related to the generation of traps at or near the Si/SiO 2 interface. This generation is due to hot and cold carriers triggering singlecarrier and multiple-carrier dissociation mechanisms [5], [6], [7]. Thus, the key information needed for proper HCD modeling is the carrier energy distribution functions (DFs), which determine the rates of both aforementioned processes. This information can be obtained from a solution of the Boltzmann transport equation (BTE) [5]. Such a solution is challenging even for planar CMOS devices with a simpler architecture and becomes extremely demanding for such devices as the LDMOS transistor. This device has a non-planar interface with a non-trivial distribution of the electric field near the bird's beak (see Figs. 1,3), where the impact ionization spot, and hence the hot-carrier degradation spot are located [3], [4].In this work we apply our physics-based HCD modelwhich has been validated using scaled CMOS transistors with a gate length as short as 65 nm [6], [7] -to represent the linear drain current change due to HCD in a high-voltage device, i.e. the nLDMOS, for the first time.

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Section: Bmentioning

confidence: 68%