Interface characteristics and electrical transport of Ge/Si heterojunction fabricated by low-temperature wafer bonding

Abstract

We report a promising method for oxide-layer-free germanium (Ge)/silicon (Si) wafer bonding based on an amorphous Ge (a-Ge) intermediate layer between Si and Ge wafers. The effect of the exposure time (te), during which the a-Ge is exposed to the air after sputtering and being taken out of the chamber on the bubble density at the bonded interface, is identified and a near-bubble-free Ge/Si bonded interface is achieved for the te of 3 s. The crystallization of a-Ge at Ge/Si bonded interface starts from a-Ge/Ge interface and it fully turns to be single-crystal Ge after post-annealing. The oxide layer at a-Ge/a-Ge bonded interface formed by the interface hydrophilic reaction disappears due to the atom redistribution triggered by the crystallization of a-Ge. As expected, the performance of the Ge/Si heterojunction diode is significantly improved by this oxide-layer-free Ge/Si bonded interface. A low dark current of 1.6 µA, high on/off current ratio of 3.4 × 105, and low ideality factor of 1.02 (150 K) is achieved at −0.5 V for the bonded Ge/Si diode. Finally, the carrier transport mechanisms at Ge/Si bonded interface annealed at different temperatures are also clearly clarified.

Strain relaxation in semiconductor wafer bonding

“…[49][50][51][52] Even for the direct semiconductor wafer bonding scheme, some amorphous layers are often observed to form between the bonded wafers. 11,[53][54][55][56][57][58] For such bonds with interfacial materials, the strain relaxation situation could be even better, resulting in lower dislocation densities, because the mediating agents may mitigate the stress due to the lattice mismatch between the bonded wafers. It is therefore required to incorporate such a stress-mitigation effect into the model to deal with various kinds of practical waferbonded structures.…”

Lateral PIN Photodiode with Germanium and Silicon Layer on SOI Wafers

“…The efficiency is defined in (3) [9,26], where Pin is the incident power, which has been considered as 100 mW/cm 2 , or 1000 W/m 2 (AM1.5) [17].…”

“…This happens because the entire silicon device has a higher open-circuit voltage. This voltage inversely depends on the diode current, which depends directly on the saturation current (Is) [9].…”

“…A disadvantage in this type of device with heterojunction is the lattice mismatch between silicon and germanium, which figures around 4.2%. Due to this difference, there is a decrease in the performance of these devices [8,9]. However, different works have demonstrated techniques that decrease the density of this threading dislocation (TD) between silicon and germanium lattices, such as the use of amorphous germanium in the bond technique [9], and methods for obtaining a high-quality germanium layer over the silicon [10].…”

Hydrophilic Direct Bonding of MgO/MgO for High-Temperature MEMS Devices

“…Si/Si, quartz/quartz, sapphire/sapphire, and so on) and heterogeneous bonding (eg. Ge/Si [32], [33], Glass/LiNbO 3 [34], GaAs/GaN [35]) instead of MgO/MgO, and the bonding mechanism has never been explored. In this paper, a hydrophilic direct bonding method of MgO/MgO that assisted by a two-step surface activation and then hightemperature annealing process was proposed for the first time.…”