Interconnections in Multi-Core Architectures: Understanding Mechanisms, Overheads and Scaling

Kumar, Rakesh; Zyuban, Victor; Tullsen, Dean M.

doi:10.1109/isca.2005.34

Cited by 242 publications

(179 citation statements)

References 21 publications

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“…Among others, Kumar et al [13] analyze several on-chip interconnection mechanisms and topologies, and quantify their area, power, and latency overheads. Their study concludes that the design choices for the interconnect have significant effect on the rest of the chip, potentially consuming a significant fraction of the real estate and power budget.…”

Section: Related Workmentioning

confidence: 99%

An energy consumption characterization of on-chip interconnection networks for tiled CMP architectures

Flores¹,

Aragón²,

Acacio³

2008

J Supercomput

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Continuous improvements in integration scale have made possible the inclusion of several processor cores on the same chip. Such designs have been named chip-multiprocessors (or CMPs) and constitute a good alternative to traditional monolithic designs for several reasons, among others, better levels of performance, scalability, and performance/energy ratio. On the other hand, higher clock frequencies and increasing number of transistors available on a single chip have revealed energy consumption as a critical design issue in current and future microarchitectures. In these architectures, the design of the on-chip interconnection network has proven to have significant impact on overall system performance and energy consumption, and that the wires used in such interconnect can be designed with varying latency, bandwidth, and power characteristics.In this work, we present a detailed characterization of the energy-efficiency of a CMP for parallel scientific applications using Sim-PowerCMP, a detailed architectural-level power-performance simulation tool for CMP architectures that integrates several well-known contemporary simulators (RSIM, Hot Leakage and Orion) into a single framework that allows precise analysis and optimization of power dissipation (both dynamic and static) taking into account performance. In this characterization, we pay special attention to the energy consumed on the interconnection network. Results for an 8-and 16-core CMP show that the most power consuming messages are the replies that carry data (almost 70% on average of the total energy consumed in the interconnect) although they represent 30% of the total number of messages. Furthermore, we show that using on-chip wires with varying latency, bandwidth, and energy characteristics can reduce the energy dissipated by the links of the interconnection network about 65% with an average impact of 10% in the execution time.

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Section: Related Workmentioning

confidence: 99%

An energy consumption characterization of on-chip interconnection networks for tiled CMP architectures

Flores¹,

Aragón²,

Acacio³

2008

J Supercomput

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“…This higher throughput comes along with the advantage of lower bandwidth requirement. Core-to-core bandwidth is likely to be a bottleneck in future CMPs [12]. Hence our proposal is better suited for the NoC like interconnects in CMPs of the future.…”

Section: G Discussion Of Resultsmentioning

confidence: 99%

Adaptive execution assistance for multiplexed fault-tolerant chip multiprocessors

Subramanyan

Singh

Saluja

et al. 2011

2011 IEEE 29th International Conference on Computer Design (ICCD)

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“…The main reason for this choice is that such interconnects allow a straightforward implementation of coherence via snooping (bus) or directory at the shared cache level (crossbar). Unfortunately, as pointed out in [20], future technology scaling will lead to on-chip interconnects having different sets of tradeoffs and design issues than traditional off-chip interconnects. In particular, wire widths and the area required by connectors do not scale down at the same rate as other features shrink, which means that either the delay or the area overheads, or both, of buses and crossbars increase as process scales.…”

Section: Current Cmps and Coherence Mechanismsmentioning

confidence: 99%

“…In particular, wire widths and the area required by connectors do not scale down at the same rate as other features shrink, which means that either the delay or the area overheads, or both, of buses and crossbars increase as process scales. In fact, the detailed study in [20] clearly shows that the area and delay overheads of buses and crossbars will become prohibitively high in CMPs with more than 16 cores in 65nm and smaller processes.…”

Section: Current Cmps and Coherence Mechanismsmentioning

confidence: 99%

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An OS-based alternative to full hardware coherence on tiled CMPs

Fensch

Cintra

2008

2008 IEEE 14th International Symposium on High Performance Computer Architecture

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The interconnect mechanisms (shared bus or crossbar) used in current chip-multiprocessors (CMPs) are expected to become a bottleneck that prevents these architectures from scaling to a larger number of cores. Tiled CMPs offer better scalability by integrating relatively simple cores with a lightweight point-to-point interconnect. However, such interconnects make snooping impractical and, thus, require alternative solutions to cache coherence. This paper proposes a novel, cost-effective mechanism to support shared-memory parallel applications that forgoes hardware maintained cache coherence. The proposed mechanism is based on the key ideas that mapping of lines to physical caches is done at the page level with OS support and that hardware supports remote cache accesses. It allows only some controlled migration and replication of data and provides a sufficient degree of flexibility in the mapping through an extra level of indirection between virtual pages and physical tiles.We evaluate the proposed tiled CMP architecture on the Splash-2 scientific benchmarks and ALPBench multimedia benchmarks against one with private caches and a distributed directory cache coherence mechanism. Experimental results show that the performance degradation is as little as 0%, and 16% on average, compared to the cache coherent architecture across all benchmarks for 16 and 32 processors.

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Interconnections in Multi-Core Architectures: Understanding Mechanisms, Overheads and Scaling

Abstract: Abstract

Cited by 242 publications

References 21 publications

An energy consumption characterization of on-chip interconnection networks for tiled CMP architectures

An energy consumption characterization of on-chip interconnection networks for tiled CMP architectures

Adaptive execution assistance for multiplexed fault-tolerant chip multiprocessors

An OS-based alternative to full hardware coherence on tiled CMPs

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