Interconnect-Aware Coherence Protocols for Chip Multiprocessors

Cheng, Liqun; Muralimanohar, Naveen; Ramani, Karthik; Balasubramonian, Rajeev; Carter, John B.

doi:10.1145/1150019.1136515

Cited by 66 publications

(70 citation statements)

References 44 publications

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“…They introduce the concept of a heterogeneous interconnect that is comprised of wires with varying area, latency, bandwidth, and energy characteristics, and they apply it to register communication within a clustered architecture. Finally, Cheng et al [7] applied the heterogeneous network concept to the cache coherence traffic problem in CMPs. In particular, they propose an interconnection network composed of three sets of wires with varying latency, bandwidth, and energy characteristics, and map coherence messages to the appropriate set taking into account their latency and bandwidth needs.…”

Section: Related Workmentioning

confidence: 99%

“…By tuning wire's characteristics, it is possible to design wires with varying latency, bandwidth, and energy properties [3]. Using links that are comprised of wires with different physical properties, a heterogeneous on-chip interconnection network is obtained [7]. With such an interconnection network, we show that the energy dissipated by the links can be reduced about 65% with an average impact of 10% in the execution time.…”

Section: Introductionmentioning

confidence: 98%

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An energy consumption characterization of on-chip interconnection networks for tiled CMP architectures

Flores¹,

Aragón²,

Acacio³

2008

J Supercomput

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Continuous improvements in integration scale have made possible the inclusion of several processor cores on the same chip. Such designs have been named chip-multiprocessors (or CMPs) and constitute a good alternative to traditional monolithic designs for several reasons, among others, better levels of performance, scalability, and performance/energy ratio. On the other hand, higher clock frequencies and increasing number of transistors available on a single chip have revealed energy consumption as a critical design issue in current and future microarchitectures. In these architectures, the design of the on-chip interconnection network has proven to have significant impact on overall system performance and energy consumption, and that the wires used in such interconnect can be designed with varying latency, bandwidth, and power characteristics.In this work, we present a detailed characterization of the energy-efficiency of a CMP for parallel scientific applications using Sim-PowerCMP, a detailed architectural-level power-performance simulation tool for CMP architectures that integrates several well-known contemporary simulators (RSIM, Hot Leakage and Orion) into a single framework that allows precise analysis and optimization of power dissipation (both dynamic and static) taking into account performance. In this characterization, we pay special attention to the energy consumed on the interconnection network. Results for an 8-and 16-core CMP show that the most power consuming messages are the replies that carry data (almost 70% on average of the total energy consumed in the interconnect) although they represent 30% of the total number of messages. Furthermore, we show that using on-chip wires with varying latency, bandwidth, and energy characteristics can reduce the energy dissipated by the links of the interconnection network about 65% with an average impact of 10% in the execution time.

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Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 98%

An energy consumption characterization of on-chip interconnection networks for tiled CMP architectures

Flores¹,

Aragón²,

Acacio³

2008

J Supercomput

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“…Kilo-NOC [8] uses also two kinds of routers, QoS-enabled and not QoS-enabled, to provide low cost, scalable and energy-efficient QoS guarantees in a network. Prior works have also investigated co-designing the NoC with caches [9] and memory controllers [10]. In particular, work in [9] examined heterogeneous wires with varying width, latency and energy, and proposed mapping coherence messages with differing latency and bandwidth characteristics onto the different wires.…”

Section: International Conference On Computer Science and Service Sysmentioning

confidence: 99%

“…Prior works have also investigated co-designing the NoC with caches [9] and memory controllers [10]. In particular, work in [9] examined heterogeneous wires with varying width, latency and energy, and proposed mapping coherence messages with differing latency and bandwidth characteristics onto the different wires. Work in [11] proposed two asymmetric networks, one customized for coherence and short messages and the other for cache bank reply packets.…”

Section: International Conference On Computer Science and Service Sysmentioning

confidence: 99%

A case of area- and energy-efficient heterogeneous mesh network-on-chip

Yan¹,

Lai²,

Lin³

2014

Proceedings of the 3rd International Conference on Computer Science and Service System

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Abstract-In this paper, based on observation on performance analysis of mesh network, we proposed a case of area-and energy-efficient heterogeneous mesh network by redistributing and reconfiguring scarce network resources, buffers, links and ports, to enhance network performance. Experimental results show that proposed network can achieve maximum saturation improvement by up to 16.7% and improve network latency by up to 35% while reduce about 31.7% router area. Experimental results also show that diagonal link is efficient design for mesh network topology.

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“…The number of banks is limited to the number of links that can be directly connected to the controller. Low-latency fat RC-based wires have been employed to speed up coherence signals in a CMP environment [10] and L1 cache access in a clustered architecture [2]. A recent paper by Li et al [23] proposes the implementation of a NUCA cache in three dimensions.…”

Section: Related Workmentioning

confidence: 99%

Interconnect design considerations for large NUCA caches

MuralimanoharNaveen

BalasubramonianRajeev

2007

SIGARCH Comput. Archit. News

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The ever increasing sizes of on-chip caches and the growing domination of wire delay necessitate significant changes to cache hierarchy design methodologies. Many recent proposals advocate splitting the cache into a large number of banks and employing a network-on-chip (NoC) to allow fast access to nearby banks (referred to as Non-Uniform Cache Architectures -NUCA). Most studies on NUCA organizations have assumed a generic NoC and focused on logical policies for cache block placement, movement, and search. Since wire/router delay and power are major limiting factors in modern processors, this work focuses on interconnect design and its influence on NUCA performance and power. We extend the widely-used CACTI cache modeling tool to take network design parameters into account. With these overheads appropriately accounted for, the optimal cache organization is typically very different from that assumed in prior NUCA studies. To alleviate the interconnect delay bottleneck, we propose novel cache access optimizations that introduce heterogeneity within the inter-bank network. The careful consideration of interconnect choices for a large cache results in a 51% performance improvement over a baseline generic NoC and the introduction of heterogeneity within the network yields an additional 11-15% performance improvement.

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Interconnect-Aware Coherence Protocols for Chip Multiprocessors

Abstract: Abstract

Cited by 66 publications

References 44 publications

An energy consumption characterization of on-chip interconnection networks for tiled CMP architectures

An energy consumption characterization of on-chip interconnection networks for tiled CMP architectures

A case of area- and energy-efficient heterogeneous mesh network-on-chip

Interconnect design considerations for large NUCA caches

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