Interaction of scaling trends in processor architecture and cooling

Abstract

It is predicted that two important trends are likely to accompany traditional CMOS semiconductor technology scalingchip multiprocessors and 3D integration. With the everincreasing power consumption and the consequent difficulty in heat removal, it is important to consider the limits and implications of different cooling methods for the upcoming manycore and 3D era. In this paper, we consider both technology scaling and manycore architecture scaling trends in conjunction with conventional air cooling and advanced microchannel cooling for both 2D and 3D microprocessors and identify interesting inflection design points down the road.

Overheat protection circuit for high frequency processors

“…It has been already shown [2] that external heat removal methods (such as air cooling, microchannel cooling and heat sinks) are limited and do not fulfil requirements of modern integrated circuits. As an effect the thermal-aware design of integrated circuits is needed.…”

Performance optimization of multi-core processors using core hopping - thermal and structural

“…Many cores particularly pose a thermal problem i.e., primary cores consume more power than the other simple cores which results in localized hot spots [10]. Cho et al [11] makes the point that at any given point of time not all cores in CMP's will be functioning i.e., design cycle level itself.…”

Temperature-Aware Architecture: Lessons and Opportunities

“…Microchannel cooling (both 2D and 3D) is an example of proximity cooling, where coolant flows through microchannels cut in the silicon substrate and provides a short heat transfer path from the heat sources to the ambient. Huang et al [10] show that although 2D microchannel can tolerate much higher power densities, increasing chip sizes pose a practical limitation as pumping coolant become much less efficient through longer microchannels [11]. All these advanced cooling solutions would allow significantly higher local power density, and favor tightly clustered cores to reduce communication latency and enable resource sharing.…”