Intelligent BSIM4 Model Parameter Extraction for Sub-100 nm MOSFETs era

Li, Yiming; Cho, Yen-Yu

doi:10.7567/ssdm.2003.a-8-3

Cited by 4 publications

(7 citation statements)

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“…For multi LTPS TFTs, development of advanced compact model and corresponding parameter optimization technique are the most important issues. We are currently working on intelligent optimization algorithms [8,9] for LTPS TFT parameter extraction.…”

Section: Discussionmentioning

confidence: 99%

“…, and output conductance (G ds ) is simultaneously performed with numerical optimization technique [9]. Compared with the measured results, the extraction is within 3% of accuracy.…”

Section: Introductionmentioning

confidence: 91%

“…A set of mobility parameters is firstly optimized for the linear region of I D − V G curves. The optimization kernel is with the Levenberg-Marquardt algorithm [9]. It is a trust-region modification of the Gauss-Newton algorithm.…”

Section: The Parameter Extraction Techniquementioning

confidence: 99%

“…Based on the physical properties of the LTPS TFTs and the mathematical behaviors of the RPI compact models [7][8][9], our approach sequentially optimizes the model parameters in the regions of linear, subthreshold, saturation, and leakage. For a set of given measured data, extraction of…”

Section: Introductionmentioning

confidence: 99%

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A Novel Approach to Compact Model Parameter Extraction for Excimer Laser Annealed Complementary Thin Film Transistors

2004

J Comput Electron

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A unified physical-based model parameter extraction technique for excimer laser annealed lower temperature polycrystalline silicon (LTPS) complementary thin film transistors (TFTs) is for the first time proposed. For two well-known compact models of LTPS TFT, Rensselaer Polytechnic Institute (RPI) V1 and V2 models, our approach sequentially optimizes the model parameters in the regions of linear, subthreshold, saturation, and leakage. Compared with the measured results, the extracted I D − V G , I D − V D , transconductance, and output conductance are within 3% of accuracy. The agreement with the experimental data is excellent for the n-and p-type LTPS TFTs with different length and width. This extraction technique bridges the fabrication of LTPS TFTs and the design of complementary system on panel circuits.

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Section: Discussionmentioning

confidence: 99%

“…, and output conductance (G ds ) is simultaneously performed with numerical optimization technique [9]. Compared with the measured results, the extraction is within 3% of accuracy.…”

Section: Introductionmentioning

confidence: 91%

Section: The Parameter Extraction Techniquementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A Novel Approach to Compact Model Parameter Extraction for Excimer Laser Annealed Complementary Thin Film Transistors

2004

J Comput Electron

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“…To assess the effect of device structure on the SNM of a 6T SRAM cell, a mixedmode simulation is directly adopted due to lack of industrial standard equivalent circuit model [19] for nanoscale SOI FinFETs. The coupled semiconductor device equations and circuit equations are iteratively solved for device electrical characteristics and SRAM's transfer characteristics.…”

Section: Simulation Methodologymentioning

confidence: 99%

Numerical Simulation of Static Noise Margin for a Six-Transistor Static Random Access Memory Cell with 32nm Fin-Typed Field Effect Transistors

Hwang

2007

Computational Science – ICCS 2007

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Abstract. We in this paper for the first time explore the static noise margin (SNM) of a six-transistor (6T) static random access memory (SRAM) cell with nanoscale silicon-on-insulator (SOI) fin-typed field effect transistors (FinFETs). The SNM is calculated with respect to the supply voltage, operating temperature, and cell ratio by performing a three-dimensional mixed-mode simulation. To include the quantum mechanical effect, the density-gradient equation is simultaneously solved in the coupled device and circuit equations. The standard deviation (σSNM ) of SNM versus device's channel length is computed, based upon the design of experiment and response surface methodology. Compared with the result of SNM for SRAM with 32nm planar metal-oxide-semiconductor field effect transistors, SRAM with SOI FinFETs quantitatively exhibits higher SNM and lower σSNM . Improvement of characteristics resulting from good channel controllability implies that SRAM cells fabricated with FinFETs continuously maintains cell stability in sub-32nm technology nodes.

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A Pattern-Based Domain Partition Approach to Parallel Optical Proximity Correction in VLSI Designs

19th IEEE International Parallel and Distributed Processing Symposium

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A novel parallel optical proximity correction (OPC) technique is proposed for process distortion compensation of layout mask in design and fabrication of very large scale integration (VLSI) circuits. Based on a genetic algorithm (GA), rule-and model-based correction methods, and domain decomposition algorithms, a parallel OPC system is successfully developed for the layout mask correction of VLSI circuits on a Linux-based PC cluster with the message passing interface (MPI) libraries. Tested on severallayout patterns, the implemented pattern-based partition scheme shows good accuracy for the OPC-corrected layout mask of VLSI designs. Computational and parallel benchmarks, such as speedup and efficiency, are achieved and exhibit excellent performance of the developed system. Our approach provides an alternative in developing advanced computer aided design (CAD) tools and benefits design and fabrication of system-on-chip (SoC).

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Intelligent BSIM4 Model Parameter Extraction for Sub-100 nm MOSFETs era

Cited by 4 publications

References 0 publications

A Novel Approach to Compact Model Parameter Extraction for Excimer Laser Annealed Complementary Thin Film Transistors

A Novel Approach to Compact Model Parameter Extraction for Excimer Laser Annealed Complementary Thin Film Transistors

Numerical Simulation of Static Noise Margin for a Six-Transistor Static Random Access Memory Cell with 32nm Fin-Typed Field Effect Transistors

A Pattern-Based Domain Partition Approach to Parallel Optical Proximity Correction in VLSI Designs

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