Integration of high-performance, low-leakage and mixed signal features into a 100 nm CMOS technology

Abstract

Low voltage operation in s u b -0 . 2 5~ requires the simultaneous integration of all components on a single chiphigh performance, low leakage and mixed-signal componentsis crucial. In this paper we present the successful integration of a low leakage gate-dielectric using a triple-gateoxide process with 16&24&52A, a low-k BEOL and mixed signal components. The 1.5V S U M cell

Simulation of intrinsic parameter fluctuations in decananometer and nanometer-scale MOSFETs

“…This requires the Green's function , where and give the location of the random charge in the depletion layer. For most calculations it is more convenient to use the two-dimensional (2-D) Fourier transform , which is defined by (1) This can be written in terms of the Green's function for both points at the interface (2) Brews [16] showed that the Green's function in the absence of screening due to electrons in the channel is given by (3) where is the average dielectric constant at the interface. The usual Fourier transform of the Coulomb potential is , and the remaining factors show how the potential is screened by image charges in the gate and by the carriers below the depletion layer.…”

“…The gate dielectric thickness in mass production MOSFETs has already reached the 1.5-nm barrier [1], [82] with sub 1-nm physical thickness utilized in the advanced research devices [5]. Atomic scale roughness of the Si/SiO and gate/SiO interfaces introduces significant intrinsic parameter fluctuations.…”

“…N the past couple of years, MOSFETs have reached decananometer (between 10 and 100 nm) dimensions with 40-50 nm physical gate length devices that are available now in the 90-nm technology node [1], [2], 35-nm transistors ready for mass production in 2 to 3 years time [3] and 15 nm [4], and even 10 nm [5] MOSFETs with conventional architecture demonstrated in a research environment. The 2001 edition of the International Technology Roadmap for Semiconductors forecasts that the MOSFET will become a nanometer scale (i.e.…”

Intrinsic parameter fluctuations in decananometer mosfets introduced by gate line edge roughness

“…N THE past couple of years, MOSFETs have reached deep decananometer (sub 50-nm) dimensions with 40-50-nm physical gate length devices developed now for the 90-nm technology node [1], [2], 35-nm transistors ready for mass production in 2-3 years time [3] and 10-nm MOSFETs with conventional architecture demonstrated in a research environment [4]. Intrinsic parameter fluctuations play an increasingly important role in such devices at a time when the fluctuation margins shrink due to reduction in supply voltage and increased transistors count per chip.…”

Design and realization of a fault-tolerant 90nm CMOS cryptographic engine capable of performing under massive defect density

“…A standard cell design of moderate complexity using a 90nm technology has been implemented in order to compare the efficiency of the reliable design methodology [6], [7]. The system consists of an implementation of the well-known Advanced Encryption Standard (AES) cryptographic algorithm using 128-bit keys [8].…”