Integration of buried insulators with high thermal conductivity in SOI MOSFETs: Thermal properties and short channel effects

Bresson, N.; Cristoloveanu, S.; Mazuré, C.; Letertre, F.; Iwai, Hiroshi

doi:10.1016/j.sse.2005.07.015

Cited by 59 publications

(41 citation statements)

References 7 publications

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“…The resulting low switchingcurrent ratios may prevent sub-45 nm gate-length transistor integration in such a platform [13]. Additionally, the thermal impedance of the thicker BOX limits electronic integration density by reducing the power budget [14]. A previously proposed, non-monolithic solution is to stack a separately fabricated photonic layer on top of the electronic circuit [15][16][17].…”

Section: Introductionmentioning

confidence: 99%

Nanophotonic integration in state-of-the-art CMOS foundries

Orcutt¹,

Khilo²,

Holzwarth³

et al. 2011

Opt. Express

124

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Abstract:We demonstrate a monolithic photonic integration platform that leverages the existing state-of-the-art CMOS foundry infrastructure. In our approach, proven XeF 2 post-processing technology and compliance with electronic foundry process flows eliminate the need for specialized substrates or wafer bonding. This approach enables intimate integration of large numbers of nanophotonic devices alongside high-density, highperformance transistors at low initial and incremental cost. We demonstrate this platform by presenting grating-coupled, microring-resonator filter banks fabricated in an unmodified 28 nm bulk-CMOS process by sharing a mask set with standard electronic projects. The lithographic fidelity of this process enables the high-throughput fabrication of second-order, wavelength-division-multiplexing (WDM) filter banks that achieve low insertion loss without post-fabrication trimming. Bienstman, D. V. Thourhout, and R. Baets, "Low-loss SOI photonic wires and ring resonators fabricated with deep UV lithography," IEEE Photon. Technol. Lett. 16(5), 1328-1330 (2004). 6. Q. Xu, B. Schmidt, S. Pradhan, and M. Lipson, "Micrometre-scale silicon electro-optic modulator," Nature 435(7040), 325-327 (2005). 7. C. Gunn, "CMOS photonics for high-speed interconnects," IEEE Micro 26(2), 58-66 (2006). 8. Y. Vlasov, W. M. J. Green, and F. Xia, "High-throughput silicon nanophotonic wavelength-insensitive switch for on-chip optical networks," Nat. Photonics 2(4), 242-246 (2008

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Section: Introductionmentioning

confidence: 99%

Nanophotonic integration in state-of-the-art CMOS foundries

Orcutt¹,

Khilo²,

Holzwarth³

et al. 2011

Opt. Express

124

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“…21,22 In this paper, the AlN-AlN direct bonding is investigated to determine its elemental composition and bonding quality as well as to verify its superiority as the buried insulator in terms of heat dissipation capability. Seamless wafer bonding has been successfully demonstrated on 150 mm Si wafer.…”

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confidence: 99%

AlN-AlN Layer Bonding and Its Thermal Characteristics

Bao

Lee

Chong

et al. 2015

ECS J. Solid State Sci. Technol.

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Homogeneous bonding was successfully demonstrated on 150 mm Si wafers by face-to-face direct dielectric bonding of clean and smooth aluminum nitride (AlN) layers. Characterization result from XPS confirms the layer composition and reveals that approximately 5 nm of the layer surface was partially oxidized during processing. After activation, substoichiometric nitrogen bound to aluminum, Al-O and Al-OH bonds were found at the thin film surface. The as-bonded wafer pairs are nearly void and particle free with a high bonding strength of 1527.8 ± 272.2 mJ/m 2 , enabling them to withstand the subsequent process steps. In addition, experimental results have indicated that the AlN-AlN bonded wafers can achieve a 23 and 16% improvement respectively in terms of heat dissipation compared with those using SiO 2 and Al 2 O 3 as the bonding layer. It is concluded that this AlN-AlN bonded wafer pairs can exhibit a better heat dissipation capability than other bonded counterparts. Wafer bonding allows heterogeneous integration of two materials that have similar or very different lattice parameters and thermal properties, via an intermediate bonding layer or direct bonding. One of the most prominent applications of wafer bonding is silicon-oninsulator (SOI), [1][2][3][4][5] and it can also be extended to germanium-oninsulator (GOI) 6,7 or other III-V groups integration. 8,9 First direct bonded SOI was reported by Lasky et al. in 1986. Since then, SOI fabricated from wafer bonding has been gaining ground from the conventional Si substrate in ultra-large scale integrations (ULSI) and micro-electro-mechanical systems (MEMS) 10 as the starting substrate, which benefits from its on-insulator structure. The "on-insulator" advantages make it possible to attain mechanical stability close to Si substrate and excellent electrostatic control, such as attenuated shortchannel effects, 11 reduced parasitic capacitance and absence of latchup. 12 As the most common buried insulator material, SiO 2 has already shown extensive popularity in a couple of optical devices. [13][14][15] However, the low thermal conductivity of SiO 2 (1.46 Wm −1 K −1 ) limits the heat dissipation efficiency and degrades the advantages of SOI. Also, the degraded heat dissipation path deteriorates its heat transfer efficiency to the underlying bulk Si layer, leading to severe self-heating effect. This effect is further magnified by device scaling for performance improvement, which constrains the applicability of SOI in electronics, especially in the cases where high temperature and power dissipation are expected. In order to address this problem, numerous efforts have been dedicated to exploring for novel buried insulator materials with high thermal conductivity such as diamond and silicon carbide. 16 Liang et al. had demonstrated the outstanding heat dissipation advantage of silicon-on-diamond (SOD) comparing to the conventional SOI substrate.17 Furthermore, high-k dielectric materials with high thermal conductivity have drawn great attention in SOI fabrication. For ...

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“…Although, SOI wafer [7,8] has shown excellent short channel characteristics, it has some disadvantages over bulk FinFETs such as high wafer cost, high defect density, heat transfer problems and may suffer from floating body problem [9]. The Bulk FinFET shows excellent promise but they do not have performance as good as SOI FinFET [10].…”

Section: Introductionmentioning

confidence: 99%

Optimization of Pie-gate Bulk FinFET Structure

Tripathi¹,

Vadthiya²,

Mishra³

2012

IJCA

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In this paper we propose a novel Pie gate bulk FinFET structure for logic applications suitable for system-on-chip (SOC) requirements. The influence of gate at bottom to junction depth, misalignment was examined for deeper junctions and shallower junctions. It has shown that bulk FinFET with source/drain to body (S/D) junctions shallower than gate at bottom has equal or better subthreshold performance than SOI FinFET. Further, we extend the concept of heavy body doping in bulk FinFETs of Pie-gate structure. The characteristics of such bulk FinFET structure is analyzed by 3D device simulation and compared with SOI FinFET. General termsBulk Fin-shaped field-effect transistor (FinFET), shortchannel performance, SS, DIBL, sentaurus TCAD device simulator.

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Integration of buried insulators with high thermal conductivity in SOI MOSFETs: Thermal properties and short channel effects

Cited by 59 publications

References 7 publications

Nanophotonic integration in state-of-the-art CMOS foundries

Nanophotonic integration in state-of-the-art CMOS foundries

AlN-AlN Layer Bonding and Its Thermal Characteristics

Optimization of Pie-gate Bulk FinFET Structure

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