Integration of an STBus Type 3 protocol custom component into a HLS tool

Tayachi, T.; Martinez, P.-Y.

doi:10.1109/dtis.2008.4540270

Cited by 3 publications

(1 citation statement)

References 0 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Since most IPs are designed to communicate through a bus, the NI uses a bus interface. There is a number of standard bus specifications to this end, such as OCP (Open Core Protocol) [27], VCI (Virtual Component Interface) [34], the AMBA family of buses such as AMBA AHB [2], AMBA AXI (Advanced eXtensible Interface) [3] for performance and low power, AMBA ACE for full cache coherency between processors and AMBA ACE-Lite for I/O coherency as well as custom buses [33].…”

Section: Noc Interface Designmentioning

confidence: 99%

NoC-Based System Integration

Tatas

Siozios

Soudris

et al. 2013

Designing 2D and 3D Network-on-Chip Architectures

View full text Add to dashboard Cite

Integrating the NoC subsystem with the core in an MPSoC is hardly trivial. It requires the design of complex NIs as well as tackle the problem of clock distribution, which requires appropriate synchronizers if the system clock cannot be distributed without skew as is often the case. The synchronizers must be reliable and yet minimize additional latency. Moreover, careful floor-planning is required to achieve good performance. Finally, any multi-and many-core environment must also efficiently solve the problem of cache coherence and therefore the NoC must support and even facilitate cache coherence mechanisms.

show abstract

Section: Noc Interface Designmentioning

confidence: 99%