In this article we present the experimental characterization of active components of a standard 65 nm CMOS technology for a temperature range from 313 to 5 K, analyzing the variation of the main parameters over temperature and voltage, recovering their main parameters (threshold voltage V th , transconductance G m and channel conductance G DS ). The measurement has been carried out wire-bonding the bare dies with the devices to a dedicated printed circuit board (PCB) that has been placed inside a dilution refrigerator. The I D -V DS curves for both NMOS and PMOS transistors shows an increase of I D in the cryogenic regime that is more relevant for high values of V GS because for lower values it is partially compensated by the variation of V th . Also, a kink is observed in these curves for high V DS values, caused by the bulk current generated by impact ionization at the drain combined with the increased resistivity of the frozen-out substrate. The transconductance G m reaches non-zero values for higher V GS as T decreases and then peaks to higher values in the cryogenic regime. In turn, G DS increases for increasing T , following the behavior observed for I D . Both results are in accordance with other thermal characterizations carried out on CMOS transistors in different technologies.