Integration Design and Process of 3-D Heterogeneous 6T SRAM with Double Layer Transferred Ge/2Si CFET and IGZO Pass Gates for 42% Reduced Cell Size

Yu, Xueyang; Chuang, Mei-Hsing; Chang, S. W.; Chang, W.-H.; Hong, T.-C.; Chiang, Chi‐Lu; Lu, Wen-Hsiang; Yang, C.-Y.; Chen, W.-J.; Lin, Jyi-Tsong; Wu, Pin-Han; Sun, Tzu-Yu; Kola, Sekhar Reddy; Yang, Yuh‐Shyong; Da, Yun; Sung, P.-J.; Wu, C.-T.; Cho, T.-C.; Luo, G.-L.; Kao, Kuo-Hsing; Chiang, Meng Hsueh; C.-Y., W.; Su, C.-J.; Chao, Tien Sheng; Maeda, Tatsuro; Samukawa, Seiji; Li, Y.; Lee, Y.-J.; Wu, W.-F.; Tarng, J. H.; Wang, Y.-H.

doi:10.1109/iedm45625.2022.10019507

Cited by 9 publications

(3 citation statements)

References 1 publication

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“…While, complementary field-effect transistor (CFET), which is 3D integration at the transistor level, is a technology that vertically stacks n-ch and p-ch FETs to create a CMOS circuit. [1][2][3][4][5][6][7][8] This improves the footprint of the CMOS circuit and shortens the wiring distance between the n-ch and p-ch FETs comprising the CMOS circuit, resulting in a faster circuit.…”

Section: Introductionmentioning

confidence: 99%

Evaluation of extremely thin polycrystalline germanium films and their TFT performance fabricated at 400 °C by Cu-induced crystallization on a glass substrate

Suzuki,

Hara

2024

Jpn. J. Appl. Phys.

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Germanium (Ge) has high mobility and is more suitable for low-temperature device processes than silicon (Si); thus, it has attracted attention as an upper-layer transistor for monolithic three-dimensional (M3D) integration. We evaluated in detail the crystalline quality of extremely thin polycrystalline-Ge (poly-Ge) thin films thinner than 15 nm fabricated by metal-induced crystallization using copper (Cu-MIC) at 400 ℃ using micro-Raman scattering, in-plane X-ray diffraction, transmission electron microscopy (TEM), TEM energy dispersive X-ray spectroscopy, and TEM electron diffraction. Additionally, the films were applied to p-ch double-gate (DG) poly-Ge thin-film transistors (TFTs), and their performance was evaluated. As a result, a high Ion/Ioff ratio of 2.8×103 was realized by crystallization at 400 ℃ with a ratio equal to that of crystallization at 500 °C. This study demonstrated the feasibility of Cu-MIC DG poly Ge TFTs for M3D applications.

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Section: Introductionmentioning

confidence: 99%

Evaluation of extremely thin polycrystalline germanium films and their TFT performance fabricated at 400 °C by Cu-induced crystallization on a glass substrate

Suzuki,

Hara

2024

Jpn. J. Appl. Phys.

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“…HE complementary field-effect-transistors (CFETs) have recently been reported through a folding of n-FET onto p-FET (or p-FET onto n-FET) for emerging VLSI technologies [1]- [5]. The first three dimensional (3-D) monolithic integration of CFETs with bottom p-FET and top n-FET was demonstrated, where the critical modules of the CFET process were discussed [1].…”

Section: Introductionmentioning

confidence: 99%

“…The first three dimensional (3-D) monolithic integration of CFETs with bottom p-FET and top n-FET was demonstrated, where the critical modules of the CFET process were discussed [1]. CFET can provide excellent electrostatic integrity by using the structure of gate-all-around (GAA) nanosheet (NS), but the fabrication process is complicated and with less repeatability during the channel etching and gate metal deposition [4], [5]. Hence, it is imperative to acknowledge that process variations wield a substantial influence on the holistic operational performance of circuits employing these devices.…”

Section: Introductionmentioning

confidence: 99%

Electrical Characteristic and Power Fluctuations of GAA Si NS CFETs by Simultaneously Considering Six Process Variation Factors

Kola,

2023

IEEE Open J. Nanotechnol.

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Characteristic variability induced by process variation effect (PVE) is one of technological challenges in semiconductor industry. In this work, we computationally study electrical characteristic and power fluctuations induced by six factors of PVE of the gate-all-around (GAA) silicon (Si) nanosheet (NS) complementary field-effect-transistors (CFETs) which are formed by vertically stacking n-FET on top of p-FET. Among the six factors, NS thickness (TNS), NS width (WNS), and gate length (LG) are identified as crucial factors contributing to large variations in device characteristics. The p-FET exhibits substantial off-state current fluctuation (about 151%) due to the bottom parasitic channel leakages. Compared with the magnitudes of dynamic and short circuit powers, the static power is marginal, but it possesses the largest fluctuation (up to 148%). If we assume that each factor of PVE has the same probability distribution as the others and all are mutually independent, the statistical sum of their power fluctuations will exhibit more than 50% overestimations, compared with the results when all factors are considered simultaneously.

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Virtual Fab Coupled Physics-Based Simulation Design of Sub-2nm Node 3D Heterogeneous Si/IGZO 6T SRAM

Di,

Zhao,

Luo

et al. 2024

2024 2nd International Symposium of Electronics Design Automation (ISEDA)

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Integration Design and Process of 3-D Heterogeneous 6T SRAM with Double Layer Transferred Ge/2Si CFET and IGZO Pass Gates for 42% Reduced Cell Size

Cited by 9 publications

References 1 publication

Evaluation of extremely thin polycrystalline germanium films and their TFT performance fabricated at 400 °C by Cu-induced crystallization on a glass substrate

Evaluation of extremely thin polycrystalline germanium films and their TFT performance fabricated at 400 °C by Cu-induced crystallization on a glass substrate

Electrical Characteristic and Power Fluctuations of GAA Si NS CFETs by Simultaneously Considering Six Process Variation Factors

Virtual Fab Coupled Physics-Based Simulation Design of Sub-2nm Node 3D Heterogeneous Si/IGZO 6T SRAM

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