Integrating sleep and pass transistor logic for leakage power reduction in FinFET circuits

Dadoria, Ajay Kumar; Khare, Kavita; Gupta, Tarun Kumar; Khare, Nilay

doi:10.1007/s10825-017-1034-3

Cited by 13 publications

(8 citation statements)

References 20 publications

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“…To resolve the issue of leakage power dissipation encountered in primitive buffer techniques, strategy of stacking is adopted , . In this approach as shown in Figure , the P‐type transistors in PUN and N‐type transistors in PDN are split up into 2 halves with both twin transistors bearing half the original transistor width.…”

Section: Performance Analysis Of Test Bench Architecturementioning

confidence: 99%

Designing of ultra‐low‐power high‐speed repeaters for performance optimization of VLSI interconnects at 32 nm

Khursheed

Khare

Haque

2018

Int J Numerical Modelling

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This paper resolves the performance issue encountered in very-large-scale integration interconnects due to downsizing of integrated circuits. Interconnects designed using carbon nanotubes (CNT) are compared with conventional copper interconnect. The propagation delay of very lengthy interconnect wires is ameliorated by interpolating smart buffers as repeaters within the wires.Existing buffer designs are contrived using both CNT and MOS technology for comparison using a different combination of MOS repeater-Cu interconnect and CNT repeater-CNT interconnect. Propound buffer uses power gating techniques and automated toggling approach to reduce delay besides mitigating average power consumption. Compared to conventional buffer, PropoundDesign3 brings about dynamic power saving of 99.94% and leakage power saving of 93%, but causes delay penalty. PropoundDesign2 saves dynamic power by 99.86% and leakage power by 88% and offers reduction in delay by 52%. Whereas PropoundDesign1 saves dynamic power by 98% and reduces propagation delay by 64% but on the cost of leakage power consumption. Simulation for 32 nm is done in HSPICE by considering a section of long interconnect line as driver interconnect load system using Stanford SPICE model for CNT and BSIM4 PTM for MOS.

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Section: Performance Analysis Of Test Bench Architecturementioning

confidence: 99%

Designing of ultra‐low‐power high‐speed repeaters for performance optimization of VLSI interconnects at 32 nm

Khursheed

Khare

Haque

2018

Int J Numerical Modelling

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“…A small I on /I off in sub‐V th circuits places tight limits on the maximum number of bits per line in ultralow power memory design. Table shows the different device parameters from H FIN (nm), W FIN (nm), L (nm), V DD , and work function of N‐type or p‐type FinFET 7 to 20‐nm technology in HP and LSTP modes …”

Section: Literature Reviewmentioning

confidence: 99%

“…Table 1 shows the different device parameters from H FIN (nm), W FIN (nm), L (nm), V DD , and work function of N-type or p-type FinFET 7 to 20-nm technology in HP and LSTP modes. 20,21 Simulations are performed at 20, 16, 14, 10, and 7 nm by using FinFET technology in LSTP model for optimization of power consumption by using HSPICE simulator, with variation of all the parameters with the scaling of technology. 22 Tables 2 and 3 show I ON and I OFF currents of N-FinFET and P-FinFET from 20 to 7-nm technologies.…”

Section: B Calculation Of I On and I Off Current Ratio (I On /I Off )mentioning

confidence: 99%

Integrating flipped drain and power gating techniques for efficient FinFET logic circuits

Dadoria

Khare

Gupta

et al. 2018

Int J Numerical Modelling

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Power dissipation is a main attention for designing complementary metal oxide semiconductor Very Large Scale Integration (VLSI) circuits in deep sub‐micron technology. Constant field device scaling leads to high transistor density, reduction in power supply, lower threshold voltage, and reduction in oxide thickness. This gives rise to short channel effects and increases the leakage currents causing power dissipation. In this paper, based on literature survey, new flipped drain gating (FDG) technique is proposed for mitigation of leakage currents; further FDG technique is integrated with power gating technique which makes power dissipation lower than FDG. Proposed techniques are integrated with FinFET technology and applied on Logic Gates and bench mark circuits on HSPICE simulator. Simulation is carried out at 27°C temperature by using 20 to 7‐nm Berkley Predictive Technology Module. Simulation results at 10‐MHz frequency shows maximum saving in leakage power using FDG technique at input vector 01 as 80.35% compared with conventional drain gating for EXOR logic. Similarly, FDG technique saves maximum dynamic power of 25.98% when compared with conventional drain gating for AND logic.

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“…Power consummation, Area requirement, leakage current and time to the market are some of the issues with the VLSI circuits and people are continuously trying to optimize these parameters through the various technological developments from time to time. As per the prophecy made by the Gordon Moore in the year 1965, number of devices or components on a single silicon chip turn out to be doubles in approximately 18-24 months from the present time [1,4].…”

Section: Introductionmentioning

confidence: 99%

Design and Analysis of CNTFET based VLSI Interconnects by Using PVT Variation

Dadoria

Garg²,

Kushwah³

et al. 2021

Preprint

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With the quick progress in the area of digital electronics results in miniaturization of semiconductor Industries. In Deep Sub Micron regime, because of leakage current, power consumption is turn out to be a major issue; hence constant efforts are being made by the researchers for investigating the various ways to minimize this. There are various methods available for the same and out of several available methods use of Carbon Nano-tube technology is a promising way to design low power circuits efficiently. Here new techniques are introduced for the reduction of leakage power. Here in this work, comparison of the main performance parameters of Copper on chip nano-interconnect with CNTFET has been done. We have measured the impact of ION and IOFF current by applying Process variation in CU and CNT- Interconnects with the variation of Tubes at 32nm technology and analysed the performance of the digital circuits with scaling of technology. The different kind of simulation outcomes indicates that by applying 10% of deviation from normal value in different device characteristics parameters such as Length of Gate (LTube) of the Tube, Width (WTube) of the Tube, Threshold Voltage (Vth) of the Tube, Thickness (tot) of Tube and Source & Drain Doping concentration with Cu and CNTFET interconnects for NFET and PFET with the variation of tubes from 1 to 16. All the experimental outcomes are achieved by using HSPICE simulator using SPICE model of CU and CNT at27oC temperature by using 32nm Berkley Predictive Technology module.

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Integrating sleep and pass transistor logic for leakage power reduction in FinFET circuits

Cited by 13 publications

References 20 publications

Designing of ultra‐low‐power high‐speed repeaters for performance optimization of VLSI interconnects at 32 nm

Designing of ultra‐low‐power high‐speed repeaters for performance optimization of VLSI interconnects at 32 nm

Integrating flipped drain and power gating techniques for efficient FinFET logic circuits

Design and Analysis of CNTFET based VLSI Interconnects by Using PVT Variation

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