Integrating message-passing and shared-memory

Kranz, David; Johnson, Kirk L.; Agarwal, Anant; Kubiatowicz, John; Lim, Beng-Hong

doi:10.1145/155332.155338

Cited by 99 publications

(24 citation statements)

References 21 publications

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“…It has been argued that shared memory is a desirable programming model since communication happens implicitly each time two threads access the same memory location. This is in contrast to a message passing programming model where the responsibility of managing communication is placed explicitly on the programmer 41 .…”

Section: Distributed Shared Memorymentioning

confidence: 99%

Multigrain shared memory

Yeung

Kubiatowicz

Agarwal

2000

ACM Trans. Comput. Syst.

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Parallel workstations, each comprising a 10-100 processor shared memory machine, promise cost-e ective general-purpose multiprocessing. This thesis explores the coupling of such small-to medium-scale shared memory multiprocessors through software over a local area network to synthesize larger shared memory systems. Multiprocessors built in this fashion are called Distributed Scalable Shared memory Multiprocessors DSSMPs .The challenge of building DSSMPs lies in seamlessly extending hardware-supported shared memory of each parallel workstation to span a cluster of parallel workstations using software only. Such a shared memory system is called Multigrain Shared Memory because it naturally supports two grains of sharing: ne-grain cache-line sharing within each parallel workstation, and coarse-grain page sharing across parallel workstations. Applications that can leverage the e cient ne-grain support for shared memory provided by each parallel workstation have the potential for high performance.This thesis makes three contributions in the context of Multigrain Shared Memory. First, it provides the design of a multigrain shared memory system, called MGS, and demonstrates its feasibility and correctness via an implementation on a 32-processor Alewife machine. Second, this thesis undertakes an in-depth application study that quanti es the extent to which shared memory applications can leverage e cient shared memory mechanisms provided by DSSMPs. The thesis begins by looking at the performance of unmodi ed shared memory programs, and then investigates application transformations that improve performance. Finally, this thesis presents an approach called Synchronization Analysis for analyzing the performance of multigrain shared memory systems. The thesis develops a performance model based on Synchronization Analysis, and uses the model to study DSSMPs with up to 512 processors. The experiments and analysis demonstrate that scalable DSSMPs can beconstructed from small-scale workstation nodes to achieve competitive performance with large-scale all-hardware shared memory systems. For instance, the model predicts that a 256-processor DSSMP built from 16-processor parallel workstation nodes achieves equivalent performance to a 128-processor all-hardware multiprocessor on a communication-intensive w orkload.

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Section: Distributed Shared Memorymentioning

confidence: 99%

Multigrain shared memory

Yeung

Kubiatowicz

Agarwal

2000

ACM Trans. Comput. Syst.

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“…It is argued that multiprocessors should support both messagepassing and shared-memory mechanisms, since one may be better than the other for certain types of tasks [8]. Messagepassing architectures are found to be suitable for applications where the data packets are large or the transfer latency is insignificant compared to other computations.…”

Section: Related Workmentioning

confidence: 99%

A shared scratchpad memory with synchronization support

Hansen

Maroun

Kristensen

et al. 2017

2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)

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Abstract-Multicore processors usually communicate via shared memory, which is backed up by a shared level 2 cache and a cache coherence protocol. However, this solution is not a good fit for real-time systems, where we need to provide tight guarantees on execution and memory access times.In this paper, we propose a shared scratchpad memory as a time-predictable communication and synchronization structure, instead of the level 2 cache. The shared on-chip memory is accessed via a time division multiplexing arbiter, isolating the execution time of load and store instructions between processing cores. Furthermore, the arbiter supports an extended time slot where an atomic load and store instruction can be executed to implement synchronization primitives. In the evaluation we show that a shared scratchpad memory is an efficient communication structure for a small number of processors; in our setup, 9 cores. Furthermore, we evaluate the efficiency of the synchronization support for implementation of classic locks.

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“…To avoid contention it is recommended to use queues over shared memory [21] [22]. In a high volume system, shared memory results in contention and therefore inhibits scaling.…”

Section: Maximizing Parallelizationmentioning

confidence: 99%

Lean and Efficient Business Tier for Performance Scaling

Natarajan¹,

Sarda²,

Srivastava³

2015

IJCA

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Large mission critical real-time legacy OLTP systems supporting the service sectors like banking, telecom, and financial services are monolithic in nature and thereby not flexible to enable business transformation which is the need of the hour due to emerging dynamic changes to business ecosystem. Broadly speaking, these large mission critical applications can be classified into three stages of activities: pre-processing, core business processing and post processing activities.This paper focuses on making the Business processing activities tier lean and efficient. By leveraging recent advances in technologies, a methodology is described by which the OLTP applications can be successfully transformed into agile systems. The methodology enables a view of the Business Tier in five dimensions. The first dimension is identifying the business"s core critical path and how to make it lean. The second dimension is how to enhance concurrency of the activities in the critical path. The third dimension is to improve the parallelism in execution of concurrency. The fourth is to separate I/O operations off the critical path. The fifth being how to minimize contentions for shared resources to ensure higher efficiencies. The paper also presents, the results of the experiments carried out by applying the above recommendation and the performance improvements to decide the optimal setup for an environment for given workload.Addressing the five dimensions of Business Tier, this paper demonstrates the transformation that can be achieved which will enable the business to be agile and respond to market ecosystem demands in a very efficient and effective manner.

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Integrating message-passing and shared-memory

Cited by 99 publications

References 21 publications

Multigrain shared memory

Multigrain shared memory

A shared scratchpad memory with synchronization support

Lean and Efficient Business Tier for Performance Scaling

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