Integrating Abstract NoC Models within MPSoC Design

Abstract

Current embedded applications are migrating from single processor-based systems to intensive data communication requiring multiprocessing. The performance demanded by these applications requires the use of heterogeneous multiprocessing architectures in a single chip (MPSoCs) endowed with complex communication infrastructures, such as Networks on Chip or NoCs. NoC parameter choices, such as network dimensioning, topology, routing algorithm, and buffer sizing then become essential aspects for optimizing the implementation of such complex systems. This paper presents NoC models that allow evaluating communication architectures through the variation of parameters during MPSoC design. Applicability of the concepts is demonstrated through two heterogeneous MPSoC case studies: an MJPEG decoder and an H.264 encoder. IntroductionMultiprocessor SoCs (MPSoCs) are emerging as one of the technologies providing a way to face the growing design complexity of embedded systems, since they provide flexibility of programming allied to specific processor architectures adapted to selected problem classes. This leads to gains in compactness, low power consumption and performance [1][2]. MPSoCs integrate hardware (HW) such as processors, memories, interconnect and special purpose modules and software (SW) like operating systems and application code. MPSoC design is usually platform-based and dominated by SW design, to achieve cost and time efficiency [3]. The amount of functionality incorporated in an MPSoCs is continuously growing. Consequently, their complexity and size also increases. Therefore, on chip communication demands rise. Industry roadmaps and research literature point that communication will be the greater challenge in future MPSoC projects, representing up to 50% of the total energy consumption, thus becoming the system performance bottleneck [4]. The way an application is partitioned and the employed communication structures directly affect system energy and performance figures. This paper proposes a flow for inserting NoC design considerations during MPSoC design. This is achieved through communication architecture model parameterization and simulation with the target application. This flow makes use of three distinct abstraction levels to model application functionality together with the hardware architecture, and allows analyzing performance for varying NoC parameters. Among NoC parameters that can be varied stand the number of routers, the routing algorithm and the MPSoC IP cores mapping on the NoC. The main contribution of this paper is the definition of abstract NoC models that can be integrated into MPSoC design flows and the demonstration of the utility of such models through the use of two real world case studies, an MJPEG decoder and an H.264 encoder.The paper is organized as follows. Section 2 presents related work in MPSoC communication modeling and evaluation. Section 3 depicts the proposed flow, and the proposed NoC models. Section 4 presents the conducted experiments, while Section 5 discusses re...

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