Integrated synapse multiplication circuit for million-neuron networks using sub-micron MOS charge pumping phenomenon

Abstract

This paper presents a novel technique for implementing synaptic computation using MOS transistors in a diode configuration to perform synaptic multiplication with the resultant output current flowing into the bulk. The circuit contains only four transistors and can be designed with minimum feature size, which offers the possibility of massively parallel networks. In addition a novel technique to use bulk current sumrnantion is introduced, which is reahzed to place all synapses being connected to the same post-synaptic neuron in the same well. As a result the possibility of million neuron networks in a single silicon chip can be obtained. 1.IntroductionThe physical implementation of LSNN ( large scale neural networks ) is a great concern for world-wide researchers because of its possibility for industrial applications such as dynamic image recognition, intelligent retina cameras and weather prediction. The neurophysicist also requires LSNN to give a powerful tool to investigate mutual neuron interactions, since the present computer simulation is limited by both memory size and CPU speed. Therefore, the fast, large, parallel and asynchronous networks are being solicited. The pulse stream technique [ll is one of the suitable candidates for this implementation. However, in the previous works [2] [3J, the number of transistors was large and the power consumption was high, which is a bottleneck of LSNN. This paper describes a novel synapse circuit configuration with the minimum number of transistor numbers and its network topology. In Section 2, the basic idea of the charge pumping effect as a frequency conversion system is described and the experimental results are presented. In Section 3, the integrated synapse multiplication circuit is proposed and its hardware architecture is presented, which will give the way to the million neuron neural computers.