Integrated nanoelectronics for the future

Chau, R.; Doyle, B.S.; Datta, Suman; Kavalieros, J.; Zhang, Kevin

doi:10.1038/nmat2014

Cited by 360 publications

(240 citation statements)

References 7 publications

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“…Moore's law [216] with recent advances such as strained silicon [217][218] and copper interconnects [219] helping to extend device scaling. Nevertheless, even with all of the recent research breakthroughs, low-k dielectrics have remained a constant impediment to the ITRS roadmap and ultimately threaten to restrict future device speeds (and dimensional scaling) [150].…”

Section: Low-k Dielectrics/proton Gated Devicesmentioning

confidence: 99%

Self-assembled templates for the generation of arrays of 1-dimensional nanostructures: From molecules to devices

Farrell

Petkov²,

Morris

et al. 2010

Journal of Colloid and Interface Science

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Self-assembled nanoscale porous architectures, such as mesoporous silica films (MPS), block copolymer films (BCP) and porous anodic aluminas (PAAs), are ideal hosts for templating one dimension (1 D) nano-entities for a wide range of electronic, photonic, magnetic and environmental applications. All three templates offer dimensional scalability and tunability over a wide range, with critical pore sizes for each system well below the 20 nm threshold [1][2][3]. Recently, research has progressed towards controlling the pore direction, orientation and long range order of these nanostructures through so called directed self-assembly (DSA). Significantly, the introduction of a wide range of top-down chemically and physically pre-patterning substrates has facilitated the DSA of nanostructures into functional device arrays. The following review begins with an overview of the fundamental aspects of self-assembly and ordering processes during the formation of PAAs, BCPs and MPS films. Special attention is given to the different ways of directing self-assembly, concentrating on properties such as uni-directional alignment, precision placement and registry of the self-assembled structures to hierarchal or top down architectures. Finally, to distinguish this review from other articles we focus on research where nanostructures have been utilised in part to fabricate arrays of functioning devices below the sub 50 nm threshold, by subtractive transfer and additive methods. Where possible, we attempt to compare and contrast the different templating approaches and highlight the strengths and/or limitations that will be important for their potential integration into downstream processes. ACCEPTED MANUSCRIPT 3 SECTION 1.0: SELF ASSEMBLY AND NANO-ARCHITETCURESThe diversity of self-assembled nanostructures and more importantly, their precise orientation within a thin film (fixed to a substrate) ultimately determines their function and overall application. A large population of research reports to date have focused on identifying these orientations and related periodicities, using x-ray and microscopy tools, as well the development of methods for readily manipulating nanostructures, such as pre-patterning of silicon substrates for the alignment of block copolymers (BCPs) [4] and mesoporous thin films (MTFs) [5] and altering the growth direction of porous anodic alumina (PAA) templates [6]. In this section, a brief synopsis of the mechanisms behind the self-assembly/organisation of each system and highlight nanoscale architectures (and orientations), which are important from a device perspective. Templated mesoporous thin filmsOrdered mesoporous powders were first discovered by researchers at the Mobil Petrochemical Corporation in 1992 and shortly after, sol-gel derived mesoporous silica films were fabricated [1,7].The first series of ordered mesoporous films were reported by Yang et al. in 1996 [8], prepared using initial surfactant concentrations above their critical micelle concentration (CMC). However the films prepared fil...

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Section: Low-k Dielectrics/proton Gated Devicesmentioning

confidence: 99%

Self-assembled templates for the generation of arrays of 1-dimensional nanostructures: From molecules to devices

Farrell

Petkov²,

Morris

et al. 2010

Journal of Colloid and Interface Science

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“…[1][2][3] More recently, there has been renewed interest in using Ge as a channel material due to its higher hole (1900 vs. 500 cm 2 /V s) and electron (3900 vs. 1400 cm 2 /V s) mobility compared to Si. [4][5][6][7] Crystalline oxides are also being considered by the semiconductor industry as next-generation high-k dielectrics.…”

Section: Introductionmentioning

confidence: 99%

Atomic layer deposition of crystalline SrHfO3 directly on Ge (001) for high-k dielectric applications

McDaniel

et al. 2015

Journal of Applied Physics

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The current work explores the crystalline perovskite oxide, strontium hafnate, as a potential high-k gate dielectric for Ge-based transistors. SrHfO3 (SHO) is grown directly on Ge by atomic layer deposition and becomes crystalline with epitaxial registry after post-deposition vacuum annealing at ∼700 °C for 5 min. The 2 × 1 reconstructed, clean Ge (001) surface is a necessary template to achieve crystalline films upon annealing. The SHO films exhibit excellent crystallinity, as shown by x-ray diffraction and transmission electron microscopy. The SHO films have favorable electronic properties for consideration as a high-k gate dielectric on Ge, with satisfactory band offsets (>2 eV), low leakage current (<10−5 A/cm2 at an applied field of 1 MV/cm) at an equivalent oxide thickness of 1 nm, and a reasonable dielectric constant (k ∼ 18). The interface trap density (Dit) is estimated to be as low as ∼2 × 1012 cm−2 eV−1 under the current growth and anneal conditions. Some interfacial reaction is observed between SHO and Ge at temperatures above ∼650 °C, which may contribute to increased Dit value. This study confirms the potential for crystalline oxides grown directly on Ge by atomic layer deposition for advanced electronic applications.

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“…O ne of the great challenges to further improve the scaling down of silicon metal oxide semiconductor field effect transistors (MOSFETs) involves the increase of carrier mobility in the channel while maintaining electrostatic integrity 1,2 . The stringent electrostatic requirements have been met in ultra-short transistors by multigate geometry, where the optimum configuration is the nanowire (NW)-like architecture with a wrapped gate 2,3 .…”

mentioning

confidence: 99%

“…The stringent electrostatic requirements have been met in ultra-short transistors by multigate geometry, where the optimum configuration is the nanowire (NW)-like architecture with a wrapped gate 2,3 . Mobility enhancement is in turn a very attractive option because it improves device performance beyond the benefits provided by scaling 1 .…”

mentioning

confidence: 99%

Top-down fabricated silicon nanowires under tensile elastic strain up to 4.5%

et al. 2012

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strained si nanowires are among the most promising transistor structures for implementation in very large-scale integration due to of their superior electrostatic control and enhanced transport properties. Realizing even higher strain levels within such nanowires are thus one of the current challenges in microelectronics. Here we achieve 4.5% of elastic strain (7.6 GPa uniaxial tensile stress) in 30 nm wide si nanowires, which considerably exceeds the limit that can be obtained using siGe-based virtual substrates. our approach is based on strain accumulation mechanisms in suspended dumbbell-shaped bridges patterned on strained si-on-insulator, and is compatible with complementary metal oxide semiconductor fabrication. Potentially, this method can be applied to any tensile prestrained layer, provided the layer can be released from the substrate, enabling the fabrication of a variety of strained semiconductors with unique properties for applications in nanoelectronics, photonics and photovoltaics. This method also opens up opportunities for research on strained materials.

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Integrated nanoelectronics for the future

Cited by 360 publications

References 7 publications

Self-assembled templates for the generation of arrays of 1-dimensional nanostructures: From molecules to devices

Self-assembled templates for the generation of arrays of 1-dimensional nanostructures: From molecules to devices

Atomic layer deposition of crystalline SrHfO3 directly on Ge (001) for high-k dielectric applications

Top-down fabricated silicon nanowires under tensile elastic strain up to 4.5%

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