Integrated Frequency Synthesis for Convergent Wireless Solutions

Abstract

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Multimode Reconfigurable Digital $\Sigma\Delta$ Modulator Architecture for Fractional-$N$ PLLs

“…The synthesizer design parameters are extracted from [17] and listed in Table III. A linear phase model of the PLL is used to evaluate the transfer of the various blocks' noises to output phase noise [2], [11], [19].…”

A Technique for Reference Spur Eradication in Fractional-N Frequency Synthesis

“…There are three distinct classic architectures for frequency synthesizers [1]. These are the direct (analog) synthesizer, the direct digital synthesizer and the indirect synthesizer.…”

“…Since using switches, it can switch between frequencies very fast. Its drawbacks include large area for the oscillators and mixers, high power consumption and limited programmability [1].…”

“…This synthesizer is very fast when switching from one frequency to another, however synthesizing radio frequencies requires the digital technology to switch at a speed that is at least a multiple of the required frequency. This results in very high power consumption and noise generation [1].…”

“…Its main drawback is that it is slow in locking to a reference frequency (i.e., slow settling time). The PLL is the most widely used architecture for frequency synthesis and is used extensively for wireless applications [1]. This is the architecture used in this thesis.…”