Integrated common‐mode inductor design for parallel interleaved converters

Hedayati, Mohammad H.

doi:10.1049/iet-pel.2015.0837

Cited by 12 publications

(5 citation statements)

References 21 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…If the PWM interleaving method is used, total harmonic distortion (THD) of the output current of the entire system can be reduced. However, due to the intentional carrier phase errors, ZSCCs inevitably occur [14][15][16][17]. Therefore, a physical suppression method such as adding a large size filter is essential [18].…”

Section: Introductionmentioning

confidence: 99%

“…In this method, since the DC voltage must be controlled by each inverter, as many voltage sensors as the number of parallel inverters are required, such that the system becomes complicated. On the other hand, there is a method of disposing passive elements having a high impedance, such as coupled inductors in the circulating current path [14,22]. In this method, as the number of inverters connected in parallel increases, the system becomes more complex and the volume also increases.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

The Circulating Current Reduction Control Method for Asynchronous Carrier Phases of Parallel Connected Inverters

Lee

Jung

2022

Energies

View full text Add to dashboard Cite

Parallel operation of inverters is one of the most effective and representative ways to increase system capacity. However, zero-sequence circulating currents occur due to the practical deviations of components constituting individual inverters in case of parallel connected inverters in which a common direct current (DC) or alternating current (AC) bus is shared. In particular, circulating currents of the high-frequency component as well as those of the low-frequency component are generated due to the asynchronization of the carriers of individual inverters. In order to suppress the circulating currents as such, the phases of the carriers should be shifted as much as the phase errors between the carriers to compensate for the phase errors. A difficulty in this phase compensation control is that when there are several pulse-width modulation (PWM) carriers, it is impossible to identify the phase of each carrier. In this paper, to overcome the problem, a method to specify the position of one of the many carriers and control the carriers and compensate for phase errors based on the relevant phase was proposed. In addition, this paper includes the analysis of circulating currents generated in the case of carrier phase errors and proposes a method to identify carrier phase errors and compensate for the relevant errors. The proposed method was verified through simulations and experiments.

show abstract

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

The Circulating Current Reduction Control Method for Asynchronous Carrier Phases of Parallel Connected Inverters

Lee

Jung

2022

Energies

View full text Add to dashboard Cite

show abstract

“…So far, many studies have been conducted to reduce CMCs; however, this paper aims to control and reduce the common mode voltage, which fortunately, reduces CMCs [5][6][7][8]. CMCs generally flow along different paths, cause unpredictable failure in some equipment such as drive controllers, encoders, tachometer, ASDs, current sensors, and other analogue devices.…”

Section: Introductionmentioning

confidence: 99%

Common mode voltage suppression in three‐phase voltage source inverters with dynamic load

Mahmoudian

Gitizadeh

Rajaei

et al. 2019

IET Power Electronics

View full text Add to dashboard Cite

This study proposes a novel pulse width modulation (PWM) algorithm to mitigate the common mode voltage (CMV) in a multi-level voltage source inverter feeding an electric machine. Dead-time effect frequently prevents the CMV not to reach zero in several switching periods. Then the electromagnetic interference noise is generated and causes bearing failure and overvoltage stress on winding insulations. The proposed strategy compensates the dead-time effect that alleviates the highamplitude rectangular pulses with extreme range of variations during high-frequency switching transitions. The existing PWM methods reduce the CMV to ±V dc /6, however by utilising the presented approach, CMV can be reduced to zero. However, the total harmonic distortion will be increased 0.3% at fundamental current harmonic rather than conventional state PWM method, which could be neglected. Simulation results and efficiency analysis imply on worthy performance of the proposed strategy to eliminate the CMV.

show abstract

“…An interleaved circuit topology integrates more power converters connected in parallel [9][10][11][12]. The switching operations for the power converters are interleaved so the effective switching frequency is multiplied and the power capacity of the output filter is reduced.…”

Section: Introductionmentioning

confidence: 99%

Interleaved multi‐level power converter for a battery energy storage system

Wu¹,

Jou²,

Chiu³

2019

IET Power Electronics

View full text Add to dashboard Cite

This study proposes an interleaved multi-level power converter (IMPC) for a battery energy storage system. The proposed IMPC is composed of two power-electronic legs. The first power-electronic leg is an interleaved multi-level leg that contains eight power-electronic switches. Four power-electronic switches constitute a two-phase interleaved switch set and these are switched in a high-frequency interleaved pulse-width modulation. The other four power-electronic switches constitute a level-selection switch set that determines the dc bus voltage for the two-phase interleaved switch set according to the magnitude of the utility voltage. The second power-electronic leg is the low-frequency switching leg, which is composed of two power-electronic switches. Since the proposed IMPC integrates the performances of the multi-level power converter and interleaved power converter, the effective switching frequency is twice the practical switching frequency and the output voltage has five voltage levels. The ripple of the output current is significantly attenuated and the power capacity of the output filter is reduced. The proposed IMPC can also be used to adjust the real and the reactive power flows, in order to control the charging/ discharging of battery sets and to compensate for the reactive power. A hardware prototype is developed to verify the performance of the proposed IMPC.

show abstract

Integrated common‐mode inductor design for parallel interleaved converters

Cited by 12 publications

References 21 publications

The Circulating Current Reduction Control Method for Asynchronous Carrier Phases of Parallel Connected Inverters

The Circulating Current Reduction Control Method for Asynchronous Carrier Phases of Parallel Connected Inverters

Common mode voltage suppression in three‐phase voltage source inverters with dynamic load

Interleaved multi‐level power converter for a battery energy storage system

Contact Info

Product

Resources

About